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passes
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memory
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memory_dff.cc
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Author
Age
Files
Lines
*
Various improvements in memory_dff pass
Clifford Wolf
2014-08-06
1
-21
/
+22
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-19
/
+19
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
1
-1
/
+1
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-1
/
+0
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
1
-15
/
+11
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-3
/
+3
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
1
-7
/
+2
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-4
/
+7
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-19
/
+19
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-19
/
+19
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
1
-1
/
+0
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
1
-8
/
+4
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-1
/
+1
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-6
/
+6
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-6
/
+6
*
Fixed log messages in memory_dff
Clifford Wolf
2014-06-01
1
-0
/
+2
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
1
-28
/
+39
*
A fix in memory_dff for write ports with static addresses
Clifford Wolf
2013-12-01
1
-10
/
+10
*
Added help messages to memory_* passes
Clifford Wolf
2013-03-01
1
-3
/
+17
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+200