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* hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-3/+27
* Use more descriptive variable name.Alberto Gonzalez2020-04-061-2/+2
* Clean up `passes/hierarchy/submod.cc`.Alberto Gonzalez2020-04-051-25/+20
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-023-31/+31
* kernel: use more ID::*Eddie Hung2020-04-022-21/+21
* Fix double deletion in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-301-1/+0
* Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-191-68/+63
* Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-37/+99
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| * Use pool instead of std::set for determinismEddie Hung2019-12-021-1/+1
| * Move \init signal for non-port signals as long as internally drivenEddie Hung2019-11-281-1/+1
| * Fix multiple driver issueEddie Hung2019-11-271-2/+7
| * Do not replace constants with same wireEddie Hung2019-11-271-7/+3
| * CleanupEddie Hung2019-11-271-5/+3
| * Check for nullptrEddie Hung2019-11-271-1/+1
| * Stray log_dumpEddie Hung2019-11-271-1/+0
| * Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-271-40/+71
| * Promote output wires in sigmap so that can be detectedEddie Hung2019-11-261-8/+4
| * Fix submod -hiddenEddie Hung2019-11-261-5/+6
| * Add -hidden option to submodEddie Hung2019-11-261-11/+25
| * Update docs with bullet pointsEddie Hung2019-11-261-10/+9
| * Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
| * submod to bitty rather bussy, for bussy wires used as input and outputEddie Hung2019-11-221-48/+39
| * Constant driven signals are also an input to submodulesEddie Hung2019-11-221-2/+10
| * OopsEddie Hung2019-11-221-1/+0
| * sigmap(wire) should inherit port_output status of POsEddie Hung2019-11-221-1/+19
* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+3
* | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-7/+14
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-3/+62
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* Adopt @cliffordwolf's suggestionEddie Hung2019-09-031-10/+3
* -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
* stoi -> atoiEddie Hung2019-08-071-3/+3
* IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
* Fix typosEddie Hung2019-08-061-5/+5
* Use IdString::begins_with()Eddie Hung2019-08-061-11/+9
* Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
* Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
* move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-1/+77
* Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
* log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1
* WIP -chparam support for hierarchy when verificEddie Hung2019-05-031-7/+24
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-182-6/+6
* Add "hdlname" attributeClifford Wolf2019-03-261-0/+2
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-1/+1
* Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to...Clifford Wolf2019-02-241-5/+1
* Address requested changes - don't require non-$ name.Jim Lawson2019-02-221-7/+7
* Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-191-9/+9
* Define basic_cell_type() function and use it to derive the cell type for arra...Jim Lawson2019-02-151-10/+40
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
* Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-5/+36
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