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* Keep modules with $assume (like $assert)Clifford Wolf2015-07-251-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-022-5/+5
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* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-2/+2
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* documentation improvementsClifford Wolf2015-03-291-1/+1
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* Added hierarchy -auto-topClifford Wolf2015-03-181-1/+33
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* Fixed bug in "hierarchy" for parametric designsClifford Wolf2015-03-041-20/+19
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* Cosmetic fixes in "hierarchy" for blackbox modulesClifford Wolf2015-02-151-2/+4
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* Fixed pattern matching in "hierarchy -generate"Clifford Wolf2015-01-041-2/+2
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-2/+2
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* Fixed off-by-one bug in "hierarchy -check" for positional module argsClifford Wolf2014-12-241-2/+2
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* Checking existence of ports in "hierarchy -check"Clifford Wolf2014-12-191-0/+13
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* Fixed bug in "hierarchy -top" with array of instancesClifford Wolf2014-11-271-3/+10
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* Added log_warning() APIClifford Wolf2014-11-091-2/+2
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* Various win32 / vs build fixesClifford Wolf2014-10-171-2/+2
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* Header changes so it will compile on VSWilliam Speirs2014-10-171-1/+5
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* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-1/+1
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* Moved patmatch() to yosys.ccClifford Wolf2014-10-101-1/+0
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* Replaced fnmatch() with patmatch()Clifford Wolf2014-10-101-5/+4
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* set "keep" on modules with $assert cells in "hierarchy"Clifford Wolf2014-09-301-0/+30
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* namespace YosysClifford Wolf2014-09-272-11/+17
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-4/+4
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* Added module->portsClifford Wolf2014-08-142-4/+5
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-1/+1
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-022-20/+20
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-1/+1
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-312-2/+2
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* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-291-1/+3
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* Using log_assert() instead of assert()Clifford Wolf2014-07-282-3/+3
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-272-36/+36
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-272-8/+8
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-5/+5
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-262-21/+23
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* Manual fixes for new cell connections APIClifford Wolf2014-07-262-5/+5
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-262-11/+11
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-262-11/+11
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-261-4/+1
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+6
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-4/+4
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-1/+1
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-222-4/+4
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-222-4/+4
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* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-201-1/+1
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* fixed cell array handling of positional argumentsClifford Wolf2014-06-071-2/+11
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* Add support for cell arraysClifford Wolf2014-06-071-0/+34
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* Implemented read_verilog -deferClifford Wolf2014-02-131-7/+19
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* Moved some passes to other source directoriesClifford Wolf2014-02-082-0/+351
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* Added hierarchy -purge_lib optionClifford Wolf2014-02-041-3/+14
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* Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))Martin Schmölzer2014-01-141-0/+1
| | | | | | This fixes compilation errors on Arch Linux. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* Added hierarchy -libdir optionClifford Wolf2014-01-141-4/+48
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-041-1/+1
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