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passes
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hierarchy
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Author
Age
Files
Lines
*
hierarchy: Convert positional parameters to named.
Marcelina KoĆcielnicka
2020-04-21
1
-3
/
+27
*
Use more descriptive variable name.
Alberto Gonzalez
2020-04-06
1
-2
/
+2
*
Clean up `passes/hierarchy/submod.cc`.
Alberto Gonzalez
2020-04-05
1
-25
/
+20
*
kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
3
-31
/
+31
*
kernel: use more ID::*
Eddie Hung
2020-04-02
2
-21
/
+21
*
Fix double deletion in `passes/hierarchy/hierarchy.cc`.
Alberto Gonzalez
2020-03-30
1
-1
/
+0
*
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
Alberto Gonzalez
2020-03-19
1
-68
/
+63
*
Merge pull request #1519 from YosysHQ/eddie/submod_po
Claire Wolf
2020-03-03
1
-37
/
+99
|
\
|
*
Use pool instead of std::set for determinism
Eddie Hung
2019-12-02
1
-1
/
+1
|
*
Move \init signal for non-port signals as long as internally driven
Eddie Hung
2019-11-28
1
-1
/
+1
|
*
Fix multiple driver issue
Eddie Hung
2019-11-27
1
-2
/
+7
|
*
Do not replace constants with same wire
Eddie Hung
2019-11-27
1
-7
/
+3
|
*
Cleanup
Eddie Hung
2019-11-27
1
-5
/
+3
|
*
Check for nullptr
Eddie Hung
2019-11-27
1
-1
/
+1
|
*
Stray log_dump
Eddie Hung
2019-11-27
1
-1
/
+0
|
*
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
Eddie Hung
2019-11-27
1
-40
/
+71
|
*
Promote output wires in sigmap so that can be detected
Eddie Hung
2019-11-26
1
-8
/
+4
|
*
Fix submod -hidden
Eddie Hung
2019-11-26
1
-5
/
+6
|
*
Add -hidden option to submod
Eddie Hung
2019-11-26
1
-11
/
+25
|
*
Update docs with bullet points
Eddie Hung
2019-11-26
1
-10
/
+9
|
*
Move \init from source wire to submod if output port
Eddie Hung
2019-11-25
1
-0
/
+7
|
*
submod to bitty rather bussy, for bussy wires used as input and output
Eddie Hung
2019-11-22
1
-48
/
+39
|
*
Constant driven signals are also an input to submodules
Eddie Hung
2019-11-22
1
-2
/
+10
|
*
Oops
Eddie Hung
2019-11-22
1
-1
/
+0
|
*
sigmap(wire) should inherit port_output status of POs
Eddie Hung
2019-11-22
1
-1
/
+19
*
|
sv: Improve handling of wildcard port connections
David Shah
2020-02-02
1
-3
/
+3
*
|
hierarchy: Correct handling of wildcard port connections with default values
David Shah
2020-02-02
1
-7
/
+14
*
|
hierarchy: Resolve SV wildcard port connections
David Shah
2020-02-02
1
-3
/
+62
|
/
*
Adopt @cliffordwolf's suggestion
Eddie Hung
2019-09-03
1
-10
/
+3
*
-auto-top should check $abstract (deferred) modules with (* top *)
Eddie Hung
2019-08-28
1
-0
/
+31
*
stoi -> atoi
Eddie Hung
2019-08-07
1
-3
/
+3
*
IdString::str().substr() -> IdString::substr()
Eddie Hung
2019-08-06
1
-1
/
+1
*
Fix typos
Eddie Hung
2019-08-06
1
-5
/
+5
*
Use IdString::begins_with()
Eddie Hung
2019-08-06
1
-11
/
+9
*
Use input default values in hierarchy pass
Clifford Wolf
2019-06-19
1
-0
/
+38
*
Refactor hierarchy wand/wor handling
Clifford Wolf
2019-05-28
1
-102
/
+143
*
move wand/wor resolution into hierarchy pass
Stefan Biereigel
2019-05-27
1
-1
/
+77
*
Add "hierarchy -chparam" support for non-verific top modules
Clifford Wolf
2019-05-03
1
-12
/
+35
*
log_warning_noprefix -> log_warning as per review
Eddie Hung
2019-05-03
1
-1
/
+1
*
WIP -chparam support for hierarchy when verific
Eddie Hung
2019-05-03
1
-7
/
+24
*
Add "whitebox" attribute, add "read_verilog -wb"
Clifford Wolf
2019-04-18
2
-6
/
+6
*
Add "hdlname" attribute
Clifford Wolf
2019-03-26
1
-0
/
+2
*
Only run derive on blackbox modules when ports have dynamic size
Clifford Wolf
2019-03-02
1
-1
/
+1
*
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to...
Clifford Wolf
2019-02-24
1
-5
/
+1
*
Address requested changes - don't require non-$ name.
Jim Lawson
2019-02-22
1
-7
/
+7
*
Fix normal (non-array) hierarchy -auto-top.
Jim Lawson
2019-02-19
1
-9
/
+9
*
Define basic_cell_type() function and use it to derive the cell type for arra...
Jim Lawson
2019-02-15
1
-10
/
+40
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-1
/
+1
*
Refactor code to avoid code duplication + added comments
Ruben Undheim
2018-10-20
1
-2
/
+5
*
Support for SystemVerilog interfaces as a port in the top level module + test...
Ruben Undheim
2018-10-20
1
-5
/
+36
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