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* Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+4
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
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* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
| | | | | No functional change, but pulls more logic out of the expand_module function.
* Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
| | | | | | | | | | I think the code is now a bit easier to follow (and has lost some levels of indentation!). The only non-trivial change is that I removed the check for cell->type[0] != '$' when deciding whether to complain if we couldn't find a module. This will always be true because of the early exit earlier in the function.
* Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-083-3/+3
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Sign extend port connections where necessaryZachary Snow2020-12-181-2/+6
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Validate parameters only when they are usedMiodrag Milanovic2020-09-251-5/+7
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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-1/+1
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Use C++11 final/override keywords.whitequark2020-06-183-6/+6
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* Merge pull request #2089 from rswarbrick/modportsclairexen2020-06-081-13/+6
|\ | | | | Simplify a modport check in hierarchy.cc
| * Simplify a modport check in hierarchy.ccRupert Swarbrick2020-05-261-13/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code originally comes from commit 458a940. When an interface is used via a modport, code in genrtlil.cc sets '\\interface_type' and '\\interface_modport' properties on the wire. In hierarchy.cc, we pick up the modport name and add it to a dict called modports_used_in_submodule (that maps connection source to modport name). Before this patch, the modport name is retrieved as a strpool and then iterated over in an arbitrary order, discarding all entries but the last. In practice, the pool will always have 0 or 1 entries because the string used to construct it is a valid identifier, so doesn't contain any pipe symbols. This patch changes the code to retrieve the modport name as just a string. This will have the same effect in practice, but may be a bit less confusing! The code also gets moved down closer to where the result is used, which might be a bit more efficient since we won't always get as far as the check. The patch also removes some commented-out code, which I think was intended to add some typechecking at some point, but was never implemented. Since this dates back to October 2018, I think it makes more sense to just take it out.
* | Fix small typos in documentation for hierarchy commandRupert Swarbrick2020-05-281-2/+2
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* hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-3/+27
| | | | Fixes #1821.
* Use more descriptive variable name.Alberto Gonzalez2020-04-061-2/+2
| | | | Co-Authored-By: whitequark <whitequark@whitequark.org>
* Clean up `passes/hierarchy/submod.cc`.Alberto Gonzalez2020-04-051-25/+20
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-023-31/+31
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* kernel: use more ID::*Eddie Hung2020-04-022-21/+21
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* Fix double deletion in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-301-1/+0
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-191-68/+63
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* Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-37/+99
|\ | | | | submod: several bugfixes
| * Use pool instead of std::set for determinismEddie Hung2019-12-021-1/+1
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| * Move \init signal for non-port signals as long as internally drivenEddie Hung2019-11-281-1/+1
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| * Fix multiple driver issueEddie Hung2019-11-271-2/+7
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| * Do not replace constants with same wireEddie Hung2019-11-271-7/+3
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| * CleanupEddie Hung2019-11-271-5/+3
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| * Check for nullptrEddie Hung2019-11-271-1/+1
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| * Stray log_dumpEddie Hung2019-11-271-1/+0
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| * Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-271-40/+71
| | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.
| * Promote output wires in sigmap so that can be detectedEddie Hung2019-11-261-8/+4
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| * Fix submod -hiddenEddie Hung2019-11-261-5/+6
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| * Add -hidden option to submodEddie Hung2019-11-261-11/+25
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| * Update docs with bullet pointsEddie Hung2019-11-261-10/+9
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| * Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
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| * submod to bitty rather bussy, for bussy wires used as input and outputEddie Hung2019-11-221-48/+39
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| * Constant driven signals are also an input to submodulesEddie Hung2019-11-221-2/+10
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| * OopsEddie Hung2019-11-221-1/+0
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| * sigmap(wire) should inherit port_output status of POsEddie Hung2019-11-221-1/+19
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* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-7/+14
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-3/+62
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Adopt @cliffordwolf's suggestionEddie Hung2019-09-031-10/+3
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* -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
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* stoi -> atoiEddie Hung2019-08-071-3/+3
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* IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
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* Fix typosEddie Hung2019-08-061-5/+5
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* Use IdString::begins_with()Eddie Hung2019-08-061-11/+9
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* Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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