iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Chenged "extensions_map" to "extensions_list" in hierarchy.cc	Clifford Wolf	2018-03-27	1	-2/+2
*	passes/hierarchy: Reduce code duplication in expand_module	Sergi Granell	2018-03-27	1	-15/+13
*	Add .sv support to "hierarchy -libdir"	Clifford Wolf	2018-03-26	1	-0/+6
*	Bugfix in hierarchy blackbox module port width handling	Clifford Wolf	2018-01-07	1	-1/+2
*	Bugfix in hierarchy handling of blackbox module ports	Clifford Wolf	2018-01-05	1	-5/+4
*	Temporarily derive blackbox modules in hierarchy to evaluate port widths	Clifford Wolf	2018-01-04	1	-1/+14
*	Add error for cell output ports that are connected to constants	Clifford Wolf	2017-07-22	1	-20/+21
*	Fix handling of empty cell port assignments (i.e. ignore them)	Clifford Wolf	2017-07-21	1	-0/+3
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-1/+1
*	Do not fix port widths on any blackbox instances	Clifford Wolf	2017-02-13	1	-1/+1
*	Do not eagerly fix port widths on parameterized cells	Clifford Wolf	2017-02-12	1	-0/+3
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-1/+1
*	passes/hierarchy: delete some dead code	Austin Seipp	2017-01-15	1	-4/+0
*	Added cell port resizing to hierarchy pass	Clifford Wolf	2017-01-01	1	-0/+56
*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-1/+1
*	Bugfix in "hierarchy -check"	Clifford Wolf	2016-11-02	1	-1/+1
*	Added avail params to ilang format, check module params in 'hierarchy -check'	Clifford Wolf	2016-10-22	1	-0/+4
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+1
*	Fixed use-after-free dict<> usage pattern in hierarchy.cc	Clifford Wolf	2016-08-16	1	-1/+3
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-1/+1
*	Made the expansion order of hierarchy deterministic	Marcus Comstedt	2016-05-22	1	-3/+3
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-4/+4
*	Cleanup abstract modules at end of "hierarchy -top"	Clifford Wolf	2016-03-21	1	-2/+0
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-5/+5
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Keep modules with $assume (like $assert)	Clifford Wolf	2015-07-25	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04	1	-2/+2
*	documentation improvements	Clifford Wolf	2015-03-29	1	-1/+1
*	Added hierarchy -auto-top	Clifford Wolf	2015-03-18	1	-1/+33
*	Fixed bug in "hierarchy" for parametric designs	Clifford Wolf	2015-03-04	1	-20/+19
*	Cosmetic fixes in "hierarchy" for blackbox modules	Clifford Wolf	2015-02-15	1	-2/+4
*	Fixed pattern matching in "hierarchy -generate"	Clifford Wolf	2015-01-04	1	-2/+2
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-2/+2
*	Fixed off-by-one bug in "hierarchy -check" for positional module args	Clifford Wolf	2014-12-24	1	-2/+2
*	Checking existence of ports in "hierarchy -check"	Clifford Wolf	2014-12-19	1	-0/+13
*	Fixed bug in "hierarchy -top" with array of instances	Clifford Wolf	2014-11-27	1	-3/+10
*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17	1	-2/+2
*	Header changes so it will compile on VS	William Speirs	2014-10-17	1	-1/+5
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	1	-1/+1
*	Moved patmatch() to yosys.cc	Clifford Wolf	2014-10-10	1	-1/+0
*	Replaced fnmatch() with patmatch()	Clifford Wolf	2014-10-10	1	-5/+4
*	set "keep" on modules with $assert cells in "hierarchy"	Clifford Wolf	2014-09-30	1	-0/+30
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-11/+13
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-4/+4
*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+2
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-15/+15
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1