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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
| commit | eae390ae17839bf0273b32149f46a2560a23d934 (patch) | |
| tree | 218b3327ef63938a762859386f23215cef83c4d3 /passes/hierarchy/hierarchy.cc | |
| parent | 66582964bc11aadf3d0783a346706d801451a13f (diff) | |
| download | yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.gz yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.bz2 yosys-eae390ae17839bf0273b32149f46a2560a23d934.zip | |
Removed $predict again
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 4bb765e75..4d1e3987b 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$predict")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume")) return cache[mod] = true; } return cache[mod]; |