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path: root/passes/hierarchy/hierarchy.cc
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* Support importing verilog configurations using VerificMiodrag Milanovic2022-11-251-1/+1
* Makes sure to set initial_top when change, fixes #3462Miodrag Milanovic2022-08-261-0/+1
* add hierarchy -smtcheckJacob Lifshay2022-06-221-7/+16
* Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+4
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
* Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
* Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* Sign extend port connections where necessaryZachary Snow2020-12-181-2/+6
* Validate parameters only when they are usedMiodrag Milanovic2020-09-251-5/+7
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-1/+1
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* Merge pull request #2089 from rswarbrick/modportsclairexen2020-06-081-13/+6
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| * Simplify a modport check in hierarchy.ccRupert Swarbrick2020-05-261-13/+6
* | Fix small typos in documentation for hierarchy commandRupert Swarbrick2020-05-281-2/+2
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* hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-3/+27
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-18/+18
* kernel: use more ID::*Eddie Hung2020-04-021-20/+20
* Fix double deletion in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-301-1/+0
* Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-191-68/+63
* sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-3/+3
* hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-7/+14
* hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-3/+62
* Adopt @cliffordwolf's suggestionEddie Hung2019-09-031-10/+3
* -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
* stoi -> atoiEddie Hung2019-08-071-3/+3
* IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
* Fix typosEddie Hung2019-08-061-5/+5
* Use IdString::begins_with()Eddie Hung2019-08-061-11/+9
* Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
* Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
* move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-1/+77
* Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
* log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1
* WIP -chparam support for hierarchy when verificEddie Hung2019-05-031-7/+24
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-5/+5
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-1/+1
* Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to...Clifford Wolf2019-02-241-5/+1
* Address requested changes - don't require non-$ name.Jim Lawson2019-02-221-7/+7
* Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-191-9/+9
* Define basic_cell_type() function and use it to derive the cell type for arra...Jim Lawson2019-02-151-10/+40
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
* Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-5/+36
* Documentation improvements etc.Ruben Undheim2018-10-131-27/+38
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+13
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-7/+165
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