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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-04 14:14:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-04 14:14:26 +0100 |
| commit | 3928482a3c4fb71b8e6ccdcb362c030eef34a479 (patch) | |
| tree | 482ea8a72c3bae5bafc377136d10426898cb8ac5 /passes/hierarchy/hierarchy.cc | |
| parent | 911c44d164e04026bd3a3a2eb1bf0c5d9cca5c19 (diff) | |
| download | yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.tar.gz yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.tar.bz2 yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.zip | |
Add $cover cell type and SVA cover() support
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f1c4a1d3b..4786aacaf 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover")) return cache[mod] = true; } return cache[mod]; |