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passes
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fsm
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fsm_extract.cc
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Author
Age
Files
Lines
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-19
/
+19
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
1
-4
/
+1
*
SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands
Clifford Wolf
2014-07-22
1
-22
/
+9
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-2
/
+2
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-19
/
+19
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-19
/
+19
*
Fixes in fsm detect/extract for better detection of non-fsm circuits
Clifford Wolf
2013-12-06
1
-3
/
+3
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
1
-1
/
+1
*
Some fixes to improve determinism
Clifford Wolf
2013-08-09
1
-24
/
+27
*
Sort ctrl signals in fsm_extract
Clifford Wolf
2013-08-08
1
-0
/
+3
*
Renamed opt_rmunused to opt_clean
Clifford Wolf
2013-06-05
1
-1
/
+1
*
Added [[CITE]] tags to abc and fsm_extract passes
Clifford Wolf
2013-03-15
1
-1
/
+6
*
Added help messages for fsm_* passes
Clifford Wolf
2013-03-01
1
-2
/
+22
*
Copy attributes from state signal to fsm cell
Clifford Wolf
2013-01-05
1
-0
/
+1
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+359