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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:14:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:14:05 +0100 |
| commit | 93a70959f3f67ffcee8159b18a5f68904e32a074 (patch) | |
| tree | 1bf68c1a36c3d126fdb396b0ea9c06bcdc2040fb /passes/fsm/fsm_extract.cc | |
| parent | a2d053694b6269bab8871a810142943fac6a3a18 (diff) | |
| download | yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.tar.gz yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.tar.bz2 yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.zip | |
Replaced RTLIL::Const::str with generic decoder method
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index d077ef4a4..dc3a9ec09 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -376,7 +376,7 @@ struct FsmExtractPass : public Pass { std::vector<RTLIL::Wire*> wire_list; for (auto &wire_it : module->wires) - if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].str != "none") + if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none") if (design->selected(module, wire_it.second)) wire_list.push_back(wire_it.second); for (auto wire : wire_list) |