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passes
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fsm
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fsm_extract.cc
Commit message (
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Author
Age
Files
Lines
*
Bugfix in fsm_extract
Clifford Wolf
2015-07-03
1
-3
/
+16
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-4
/
+4
*
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf
2015-04-29
1
-1
/
+3
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
1
-1
/
+1
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
1
-8
/
+8
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-0
/
+4
*
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
Clifford Wolf
2014-08-30
1
-0
/
+10
*
Improved handling of $pmux cells in fsm_extract
Clifford Wolf
2014-08-30
1
-20
/
+75
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
1
-1
/
+1
*
Another fsm_extract bugfix
Clifford Wolf
2014-08-08
1
-0
/
+4
*
Fixed fsm_extract for wreduced muxes
Clifford Wolf
2014-08-08
1
-8
/
+25
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
1
-2
/
+2
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-17
/
+17
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
1
-2
/
+2
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-5
/
+5
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-3
/
+3
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
1
-4
/
+1
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-19
/
+19
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-19
/
+19
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
1
-4
/
+1
*
SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands
Clifford Wolf
2014-07-22
1
-22
/
+9
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-2
/
+2
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-19
/
+19
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-19
/
+19
*
Fixes in fsm detect/extract for better detection of non-fsm circuits
Clifford Wolf
2013-12-06
1
-3
/
+3
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
1
-1
/
+1
*
Some fixes to improve determinism
Clifford Wolf
2013-08-09
1
-24
/
+27
*
Sort ctrl signals in fsm_extract
Clifford Wolf
2013-08-08
1
-0
/
+3
*
Renamed opt_rmunused to opt_clean
Clifford Wolf
2013-06-05
1
-1
/
+1
*
Added [[CITE]] tags to abc and fsm_extract passes
Clifford Wolf
2013-03-15
1
-1
/
+6
*
Added help messages for fsm_* passes
Clifford Wolf
2013-03-01
1
-2
/
+22
*
Copy attributes from state signal to fsm cell
Clifford Wolf
2013-01-05
1
-0
/
+1
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+359