Changed a lot of code to the new RTLIL::Wire constructors

1 files changed, 1 insertions, 4 deletions

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index ff3ac7608..51a4a75e7 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -296,10 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 		RTLIL::Cell *cell = module->cells.at(cellport.first);
 		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
-		RTLIL::Wire *unconn_wire = new RTLIL::Wire;
-		unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
-		unconn_wire->width = unconn_sig.size();
-		module->wires[unconn_wire->name] = unconn_wire;
+		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
 		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
 	}
 }