iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add "setundef -undef"	Clifford Wolf	2018-03-12	1	-0/+11
*	Add "setundef -anyseq"	Clifford Wolf	2017-05-28	1	-2/+42
*	Improve write_aiger handling of unconnected nets and constants	Clifford Wolf	2017-05-28	1	-1/+1
*	Bugfix in "setundef" pass	Clifford Wolf	2016-11-08	1	-2/+7
*	Added "setundef -init"	Clifford Wolf	2016-06-03	1	-5/+89
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-2/+2
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-29/+28
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
*	Improved setundef random number generator	Clifford Wolf	2014-01-18	1	-1/+1
*	Added setundef command	Clifford Wolf	2014-01-17	1	-0/+157