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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
commit | cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch) | |
tree | 2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/cmds/setundef.cc | |
parent | 665759fceee4a0db3e776b7912e976eea2ff29a3 (diff) | |
download | yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.tar.gz yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.tar.bz2 yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.zip |
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/cmds/setundef.cc')
-rw-r--r-- | passes/cmds/setundef.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 6c4bb16c0..e1005a270 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -135,7 +135,7 @@ struct SetundefPass : public Pass { CellTypes ct(design); for (auto &it : module->cells) - for (auto &conn : it.second->connections) + for (auto &conn : it.second->connections_) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_signals.del(sigmap(conn.second)); @@ -144,7 +144,7 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - module->connections.push_back(RTLIL::SigSig(c, bits)); + module->connections_.push_back(RTLIL::SigSig(c, bits)); } } |