iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Major rewrite of wire selection in setundef -init	Clifford Wolf	2019-06-05	1	-30/+89
*	Indent fix	Clifford Wolf	2019-06-05	1	-23/+25
*	initialize more registers in setundef -init	Jakob Wenzel	2019-05-09	1	-16/+23
*	Hotfix for 4c82ddf	Clifford Wolf	2019-02-21	1	-11/+2
*	Add -params mode to force undef parameters in selected cells.	Keith Rothman	2019-02-21	1	-0/+29
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	Minor revision to -expose in setundef pass	Aman Goel	2018-09-10	1	-1/+7
*	Revision to expose option in setundef pass	Aman Goel	2018-08-18	1	-154/+123
*	Merge pull request #3 from YosysHQ/master	Aman Goel	2018-08-18	1	-2/+2
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\| *	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
* \|	Merging with official repo	Aman Goel	2018-07-04	1	-22/+46
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\| *	Add setundef -anyseq / -anyconst support to -undriven mode	Clifford Wolf	2018-06-01	1	-3/+11
\| *	Add "setundef -anyconst"	Clifford Wolf	2018-06-01	1	-20/+41
* \|	Correction to -expose with setundef	Aman Goel	2018-05-15	1	-0/+1
* \|	Minor correction	Aman Goel	2018-05-14	1	-2/+1
* \|	Corrections to option -expose in setundef pass	Aman Goel	2018-05-13	1	-16/+141
* \|	Add option -expose to setundef pass	Aman Goel	2018-05-13	1	-6/+26
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*	Some cleanups in setundef.cc	Clifford Wolf	2018-05-13	1	-0/+7
*	Add "setundef -undef"	Clifford Wolf	2018-03-12	1	-0/+11
*	Add "setundef -anyseq"	Clifford Wolf	2017-05-28	1	-2/+42
*	Improve write_aiger handling of unconnected nets and constants	Clifford Wolf	2017-05-28	1	-1/+1
*	Bugfix in "setundef" pass	Clifford Wolf	2016-11-08	1	-2/+7
*	Added "setundef -init"	Clifford Wolf	2016-06-03	1	-5/+89
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-2/+2
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-29/+28
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
*	Improved setundef random number generator	Clifford Wolf	2014-01-18	1	-1/+1
*	Added setundef command	Clifford Wolf	2014-01-17	1	-0/+157