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* Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
* Indent fixClifford Wolf2019-06-051-23/+25
* initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
* Hotfix for 4c82ddfClifford Wolf2019-02-211-11/+2
* Add -params mode to force undef parameters in selected cells.Keith Rothman2019-02-211-0/+29
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
* Revision to expose option in setundef passAman Goel2018-08-181-154/+123
* Merge pull request #3 from YosysHQ/masterAman Goel2018-08-181-2/+2
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| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* | Merging with official repoAman Goel2018-07-041-22/+46
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| * Add setundef -anyseq / -anyconst support to -undriven modeClifford Wolf2018-06-011-3/+11
| * Add "setundef -anyconst"Clifford Wolf2018-06-011-20/+41
* | Correction to -expose with setundefAman Goel2018-05-151-0/+1
* | Minor correctionAman Goel2018-05-141-2/+1
* | Corrections to option -expose in setundef passAman Goel2018-05-131-16/+141
* | Add option -expose to setundef passAman Goel2018-05-131-6/+26
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* Some cleanups in setundef.ccClifford Wolf2018-05-131-0/+7
* Add "setundef -undef"Clifford Wolf2018-03-121-0/+11
* Add "setundef -anyseq"Clifford Wolf2017-05-281-2/+42
* Improve write_aiger handling of unconnected nets and constantsClifford Wolf2017-05-281-1/+1
* Bugfix in "setundef" passClifford Wolf2016-11-081-2/+7
* Added "setundef -init"Clifford Wolf2016-06-031-5/+89
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* namespace YosysClifford Wolf2014-09-271-0/+4
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-29/+28
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-2/+2
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-2/+2
* Improved setundef random number generatorClifford Wolf2014-01-181-1/+1
* Added setundef commandClifford Wolf2014-01-171-0/+157