iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	rtlil: Make Process handling more uniform with Cell and Wire.	Marcelina Kościelnicka	2021-07-12	1	-6/+4
\| \| \| \| \| \|	- add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	kernel/rtlil: Extract some helpers for checking memory cell types.	Marcelina Kościelnicka	2021-05-22	1	-1/+1
\| \| \| \| \| \|	There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
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*	Clean up `passes/cmds/delete.cc`.	Alberto Gonzalez	2020-04-06	1	-24/+19
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*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-2/+2
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*	More use of IdString::in()	Eddie Hung	2019-08-15	1	-1/+1
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*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
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*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-2/+2
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*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-2/+2
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*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26	1	-4/+4
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-4/+4
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-3/+5
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-3/+3
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-3/+3
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-30/+5
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-5/+4
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-2/+3
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-1/+1
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-1/+1
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*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09	1	-5/+36
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*	Bugfix in delete command	Clifford Wolf	2014-02-09	1	-1/+3
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*	Added delete command	Clifford Wolf	2014-02-02	1	-0/+134