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* stat: pass down quiet argN. Engelhardt2023-02-281-1/+1
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* Merge pull request #2995 from georgerennie/cover_precondJannis Harder2023-02-141-0/+19
|\ | | | | chformal: Add -coverenable option
| * chformal: Note about using -coverenable with the Verific frontendJannis Harder2023-02-141-0/+5
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| * chformal: Rename -coverprecond to -coverenableGeorge Rennie2022-06-181-4/+4
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| * chformal: Test -coverprecond and reuse the src attributeJannis Harder2022-06-181-2/+2
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| * chformal: Add -coverprecond optionGeorge Rennie2022-06-181-0/+14
| | | | | | | | | | This inserts $cover cells to cover the enable signal (precondition) for the selected formal cells.
* | Merge pull request #3625 from povik/show_cleanupN. Engelhardt2023-02-061-56/+82
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| * | passes: show: s/pos/bitpos/ for readabilityMartin Povišer2023-01-131-4/+5
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Reuse string parts in generation of portboxesMartin Povišer2023-01-131-2/+5
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Touch chunk iteration in gen_portboxMartin Povišer2023-01-131-8/+11
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Label no_signode flagMartin Povišer2023-01-131-20/+19
| | | | | | | | | | | | | | | | | | Label the flag and rearrange the control flow a bit. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Simplify wire bit range logicMartin Povišer2023-01-131-8/+10
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Factor out 'join_label_pieces'Martin Povišer2023-01-131-20/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In two places, we are joining label pieces by a '|' separator. We go about it by putting the separator behind each entry, then removing the trailing separator in a final fixup pass on the built string. For easier reading, replace those occurrences by a new factored-out 'join_label_pieces' function. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Label signed_suffix flagMartin Povišer2023-01-131-3/+6
| | | | | | | | | | | | | | | | | | To make it easier to follow what's going on. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: s/idx/dot_idx/ for readabilityMartin Povišer2023-01-131-7/+7
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Fix portbox bit ranges in case of driven signalsMartin Povišer2023-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the 'show' pass generates portboxes to detail the connection of cell ports to wires, it has special handling of signal chunk repetitions, but those repetitions are not accounted for in the displayed bit range in case of cell outputs. Fix that, and so bring it into consistence with the behavior on cell inputs. So, taking for example the following Verilog snippet, module DRIVER (Q); output [7:0] Q; assign Q = 8'b10101010; endmodule module main; wire w; DRIVER driver(.Q({8{w}})); endmodule make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox instead of '7:7 - 8x 0:0' which it displayed formerly. Signed-off-by: Martin Povišer <povik@cutebit.org>
* | | Merge pull request #3624 from jix/sim_ywMiodrag Milanović2023-01-232-2/+11
|\ \ \ | | | | | | | | Changes to support SBY trace generation with the sim command
| * | | xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundefJannis Harder2023-01-112-2/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | This adds the xprop_decoder attribute to bwmuxes that drive the original unencoded signals. Setundef is changed to ignore the x inputs of these bwmuxes, so that they survive the prep script of SBY's formal flow. This is required to make simulation (via sim) using the prep model show the decoded x signals instead of 0/1 values made up by the solver.
* | | Merge pull request #3629 from YosysHQ/micko/clang_fixesMiodrag Milanović2023-01-232-1/+5
|\ \ \ | | | | | | | | Fixes for some of clang scan-build detected issues
| * | | Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-172-1/+5
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* | | show: Remove left-in debug log_warninggatecat2023-01-231-1/+0
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Improve splitcells passClaire Xenia Wolf2023-01-181-52/+120
|/ / | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Merge pull request #3605 from gadfort/stat-json-areaN. Engelhardt2023-01-111-0/+3
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| * | stat: ensure area is included in json outputPeter Gadfort2022-12-291-0/+3
| | | | | | | | | | | | Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
* | | Merge branch 'master' into claire/eqystuffClaire Xen2023-01-112-8/+8
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| * \ \ Merge pull request #3537 from jix/xpropJannis Harder2023-01-112-0/+1199
| |\ \ \ | | | | | | | | | | New xprop pass
| * | | | Deprecate gcc-4.8Miodrag Milanovic2023-01-112-8/+8
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* | | | Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2023-01-112-2/+15
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| * | | stat: Fix JSON output for empty designsJannis Harder2022-12-021-2/+2
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| * | | tee: Allow logging command output to a given scratchpad valueJannis Harder2022-12-021-0/+13
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* | | | xprop: Improve signal splitting codeJannis Harder2022-12-121-14/+10
| | | | | | | | | | | | | | | | | | | | Avoid splitting output ports twice when combining -split-outputs with -split-public and clean up the corresponding code.
* | | | Improvements in "viz" passClaire Xenia Wolf2022-12-091-24/+100
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2022-12-081-0/+39
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| * | | | xprop: Add -split-public optionJannis Harder2022-12-081-0/+39
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* | | | | Improvements in "viz" commandClaire Xenia Wolf2022-12-071-17/+51
|/ / / / | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Improvements in "viz" passClaire Xenia Wolf2022-12-071-313/+453
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Various improvements in "viz" commandClaire Xenia Wolf2022-12-061-72/+242
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Bugfix in splitcells passClaire Xenia Wolf2022-12-061-5/+13
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Improvements in "viz" commandClaire Xenia Wolf2022-12-041-45/+196
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Add "viz" pass for visualizing big-picture data flow in larger designsClaire Xenia Wolf2022-12-042-0/+511
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Add splitcells passClaire Xenia Wolf2022-12-042-0/+192
| |/ / |/| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | New xprop pass to encode 3-valued x-propagation using 2-valued logicJannis Harder2022-11-302-0/+1199
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* | Rst docs conversion (#3496)KrystalDelusion2022-11-151-0/+2
| | | | | | Rst docs conversion
* | remove extra space in formatingKamyar Mohajerani2022-09-221-2/+2
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* | stat: add tech tech-specific utilizations to jsonKamyar Mohajerani2022-09-221-65/+91
| | | | | | | | | | - refactor resource util. estimation/calculations for Xilinx and CMOS - don't print log_header if "-json" is set
* | Merge pull request #3449 from YosysHQ/aki/show_pathrwN. Engelhardt2022-08-251-0/+1
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| * | yosys: passes: cmds: show: added filename re-writing to `show -lib`Aki Van Ness2022-08-221-0/+1
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* | | Fitting help messages to 80 character widthKrystalDelusion2022-08-247-48/+54
|/ / | | | | | | | | | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* | rename: Add -witness modeJannis Harder2022-08-161-0/+81
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* | setundef: Do not add anyseq / anyconst to unused memory port clocksJannis Harder2022-08-161-0/+24
| | | | | | | | Instead set those unused clocks to zero.
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