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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-272-3/+3
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-6/+6
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-34/+34
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-262-22/+8
* Manual fixes for new cell connections APIClifford Wolf2014-07-262-2/+2
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-262-48/+48
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-262-48/+48
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-252-50/+16
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-19/+19
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-3/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-30/+23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-231-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-222-39/+39
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-222-39/+39
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-121-1/+1
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-2/+7
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-111-1/+1
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-091-2/+2
* Added abc -keepff optionClifford Wolf2014-02-141-5/+18
* updated default ABC command stringsClifford Wolf2014-02-131-4/+4
* Updated ABCClifford Wolf2014-02-131-0/+23
* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-131-4/+4
* Updated ABC and some related changesClifford Wolf2014-02-131-10/+31
* Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-121-4/+49
* Added support for "keep" attribute to abc passClifford Wolf2014-02-081-1/+1
* Re-enabled abc "retime" after sorting yout the yosys-bigsim problemClifford Wolf2014-02-071-7/+0
* Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim fa...Clifford Wolf2014-02-061-0/+7
* Added "retime" to standard ABC recipesClifford Wolf2014-02-061-4/+4
* Added support for inline commands to abc -scriptClifford Wolf2014-02-041-39/+75
* Fixed use of limited length buffer in ABC blif parserClifford Wolf2013-12-311-7/+16
* Added abc -dff and -clk supportClifford Wolf2013-12-313-34/+173
* Now using BLIF as ABC input formatClifford Wolf2013-12-311-37/+54
* Always use BLIF as ABC output formatClifford Wolf2013-12-315-268/+31
* Tighter integration of ABC buildClifford Wolf2013-11-271-0/+2
* Updated abcClifford Wolf2013-11-211-10/+27
* Renamed temp module generated by "abc" pass from "logic" to "netlist"Clifford Wolf2013-11-192-6/+6
* Fixed abc pass blif parser for constant bitsClifford Wolf2013-11-131-18/+57
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-201-4/+4
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-234-14/+255
* Added support for "assign" statements in abc vlparseClifford Wolf2013-06-152-2/+39
* Look for yosys-abc and yosys-svgviewer where the main exe isClifford Wolf2013-06-091-1/+1
* Added "make abc" and "make install-abc"Clifford Wolf2013-06-081-3/+4
* Fixed a gcc vs. clang determinism problem in abc passClifford Wolf2013-05-231-4/+11
* Fixed abc eeror handlingClifford Wolf2013-03-181-2/+2
* fixed typosJohann Glaser2013-03-181-3/+3
* Fixed strerrno vs. strerror types in ABC passClifford Wolf2013-03-171-4/+4
* Cleaned up ABC file/io error handlingClifford Wolf2013-03-171-15/+13
* added error checking at execution of ABCJohann Glaser2013-03-171-1/+19
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