| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | abc/blifparse files reorganization | Clifford Wolf | 2015-05-17 | 1 | -1539/+0 |
| * | Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types | Clifford Wolf | 2015-04-05 | 1 | -0/+88 |
| * | Fixed detection of absolute paths in ABC for win32 | Clifford Wolf | 2015-03-22 | 1 | -3/+3 |
| * | Fixed typos found by lintian | Ruben Undheim | 2015-02-01 | 1 | -1/+1 |
| * | Added "abc -lut w1:w2" | Clifford Wolf | 2015-01-15 | 1 | -5/+21 |
| * | Fixed typo in ABC command | Clifford Wolf | 2014-12-30 | 1 | -2/+2 |
| * | Less verbose ABC output | Clifford Wolf | 2014-12-29 | 1 | -20/+53 |
| * | Improved ABC clock domain partitioning | Clifford Wolf | 2014-12-23 | 1 | -2/+59 |
| * | Added "abc -markgroups" | Clifford Wolf | 2014-12-23 | 1 | -0/+20 |
| * | Added support for multiple clock domains to "abc" pass | Clifford Wolf | 2014-12-21 | 1 | -64/+123 |
| * | Fixed "abc" pass for clk and enable signals driven by logic | Clifford Wolf | 2014-12-21 | 1 | -6/+8 |
| * | Added DFFE support to "abc" pass | Clifford Wolf | 2014-12-20 | 1 | -11/+78 |
| * | Also look for yosys-abc in parent dir on win32 | Clifford Wolf | 2014-10-18 | 1 | -0/+5 |
| * | Header changes so it will compile on VS | William Speirs | 2014-10-17 | 1 | -2/+5 |
| * | More win32/abc fixes | Clifford Wolf | 2014-10-12 | 1 | -38/+33 |
| * | Added make_temp_{file,dir}() and remove_directory() APIs | Clifford Wolf | 2014-10-12 | 1 | -31/+15 |
| * | Using stringf() instead of asprintf() in "abc" pass | Clifford Wolf | 2014-10-12 | 1 | -29/+24 |
| * | Added run_command() api to replace system() and popen() | Clifford Wolf | 2014-10-12 | 1 | -73/+70 |
| * | Added API for generic cell cost calculations | Clifford Wolf | 2014-10-09 | 1 | -15/+16 |
| * | Added $_BUF_ cell type | Clifford Wolf | 2014-10-03 | 1 | -3/+7 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Small improvements in "abc" command handle_loops() function | Clifford Wolf | 2014-09-19 | 1 | -6/+9 |
| * | Using "NOT" instead of "INV" as cell name in default abc genlib file | Clifford Wolf | 2014-09-19 | 1 | -2/+2 |
| * | Do not run "scorr" in "abc -fast" | Clifford Wolf | 2014-09-18 | 1 | -4/+4 |
| * | Added "abc -fast" | Clifford Wolf | 2014-09-18 | 1 | -6/+31 |
| * | Fixed $_NOR vs. $_NOR_ typo in abc.cc | Clifford Wolf | 2014-09-16 | 1 | -1/+1 |
| * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 | 1 | -25/+161 |
| * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 1 | -2/+2 |
| * | Added "abc -D" for setting delay target | Clifford Wolf | 2014-08-14 | 1 | -5/+18 |
| * | Filter ANSI escape sequences from ABC output | Clifford Wolf | 2014-08-13 | 1 | -0/+15 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -32/+32 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -5/+4 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -6/+6 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -26/+26 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -6/+2 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -42/+42 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -42/+42 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -32/+10 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -19/+19 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -30/+23 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -34/+34 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -34/+34 |
