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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
| commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/abc/abc.cc | |
| parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
| download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip | |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/abc/abc.cc')
| -rw-r--r-- | passes/abc/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index c53c44503..4d9a6c136 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std assert(c.width == 1); newsig.append(module->wires[remap_name(c.wire->name)]); } - cell->connections()[conn.first] = newsig; + cell->set(conn.first, newsig); } design->select(module, cell); } |