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* split CodingReadme into multiple filesN. Engelhardt2021-03-221-5/+6
* bugpoint: add runner optionZachary Snow2021-03-171-0/+3
* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-0/+5
* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-2/+3
* Update command-reference-manual.texClaire Xen2021-03-041-4/+4
* RTLIL Documentation: switch in process is optionalRobert Baruch2021-02-271-1/+1
* Further juggles the wording of "character".Robert Baruch2020-11-251-1/+1
* Clarifies how character encodings work.Robert Baruch2020-11-251-5/+5
* Clarifies whitespace and eol.Robert Baruch2020-11-251-2/+6
* Cleans up doublequotesRobert Baruch2020-11-251-2/+2
* Clarifies use of integers, and character set.Robert Baruch2020-11-251-4/+12
* Clarifies processes, corrects some attributesRobert Baruch2020-11-251-29/+46
* Refactors for attributes.Robert Baruch2020-11-241-50/+50
* Cleans up some descriptions and syntaxRobert Baruch2020-11-241-25/+43
* Adds missing "end" and eol to module.Robert Baruch2020-11-221-1/+1
* Update to Values #2Robert Baruch2020-11-221-1/+1
* Update to Values sectionRobert Baruch2020-11-221-2/+2
* Adds appendix on RTLIL text formatRobert Baruch2020-11-223-0/+260
* manual: fix typo.whitequark2020-08-271-1/+1
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-263-16/+14
* Add latches to the manual.Marcelina Kościelnicka2020-06-261-42/+165
* Add a few more gate types to the manual.Marcelina Kościelnicka2020-06-261-8/+36
* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-28/+178
* Use C++11 final/override keywords.whitequark2020-06-182-4/+4
* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+7
* Use in-tree include directory in manual buildXiretza2020-05-301-1/+4
* Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-292-1/+24
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| * Document division and modulo cellsXiretza2020-05-281-0/+23
| * Add flooring division operatorXiretza2020-05-281-1/+1
| * Add flooring modulo operatorXiretza2020-05-281-1/+1
* | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-291-3/+6
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* Update CHANGELOG and manual for departure from upstreamEddie Hung2020-04-271-2/+3
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-198/+2300
* fix typo in `write_smt2` helpTeguh Hofstee2020-03-231-1/+1
* manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
* Merge pull request #1553 from whitequark/manual-dffxClaire Wolf2020-01-281-11/+90
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| * manual: document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells.whitequark2019-12-051-11/+90
* | Merge pull request #1575 from rodrigomelo9/masterEddie Hung2019-12-151-2/+2
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| * | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-2/+2
* | | Merge pull request #1577 from gromero/for-yosysEddie Hung2019-12-151-1/+1
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| * | manual: Fix text in Abstract sectionGustavo Romero2019-12-111-1/+1
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* / manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-1/+1
* manual: explain the purpose of `sync always`.whitequark2019-07-021-2/+3
* Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
* Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-1/+1
* Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-231-0/+4
* manual: document some gates.whitequark2019-01-141-9/+11
* manual: explain $tribuf cell.whitequark2019-01-141-0/+10
* Fix typo in manualClifford Wolf2019-01-071-1/+1
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