iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	2	-0/+103
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	11	-597/+653
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*	Added "yosys -A"	Clifford Wolf	2014-07-31	1	-1/+10
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*	Added "yosys -Q"	Clifford Wolf	2014-07-31	1	-26/+35
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-0/+3
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*	Added write_file command	Clifford Wolf	2014-07-30	2	-5/+7
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*	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	Clifford Wolf	2014-07-30	1	-36/+39
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*	Added "log_dump_val_worker(char *v)"	Clifford Wolf	2014-07-30	1	-0/+1
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*	Added "kernel/yosys.h" and "kernel/yosys.cc"	Clifford Wolf	2014-07-30	7	-60/+132
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*	Added "test_cell" command	Clifford Wolf	2014-07-29	1	-1/+1
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	1	-1/+3
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	2	-0/+10
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	5	-19/+75
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	2	-1/+3
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	12	-144/+157
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*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	2	-0/+15
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*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	2	-4/+42
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-1/+2
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-0/+5
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*	Small improvements in PerformanceTimer API	Clifford Wolf	2014-07-27	1	-6/+7
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	1	-0/+103
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*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27	1	-9/+26
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*	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27	1	-0/+18
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*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	3	-4/+6
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*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	2	-2/+20
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*	Added RTLIL::Design::modules()	Clifford Wolf	2014-07-27	1	-0/+3
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	4	-20/+20
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*	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27	1	-0/+15
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*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	2	-7/+111
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*	Using std::move() in SigSpec move constructor	Clifford Wolf	2014-07-27	1	-4/+4
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*	Added RTLIL::SigSpec move constructor and move assignment operator	Clifford Wolf	2014-07-27	1	-0/+15
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*	Mostly cosmetic changes to rtlil.h	Clifford Wolf	2014-07-27	1	-17/+57
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	5	-17/+17
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	5	-27/+27
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-7/+23
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-0/+43
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*	Added support for here documents	Clifford Wolf	2014-07-26	3	-18/+63
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	3	-8/+14
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-11/+11
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	5	-179/+179
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26	2	-9/+9
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*	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26	2	-0/+6
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*	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26	2	-0/+6
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*	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26	2	-17/+63
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*	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26	2	-0/+71
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*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	6	-190/+211
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	2	-8/+12
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	2	-4/+54
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*	Added RTLIL::SigSpec is_chunk()/as_chunk() API	Clifford Wolf	2014-07-25	2	-0/+20
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