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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 02:11:57 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 02:11:57 +0200 |
commit | 7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79 (patch) | |
tree | 5379a50d3fee9c33925ba1bcd462ca746e055d56 /kernel | |
parent | c91570bde32d59679ea8b72ed041ef8f6bb0d51a (diff) | |
download | yosys-7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79.tar.gz yosys-7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79.tar.bz2 yosys-7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79.zip |
Added RTLIL::SigSpec move constructor and move assignment operator
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f235b1de5..97d01617a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -625,6 +625,21 @@ public: SigSpec(std::vector<RTLIL::SigBit> bits); SigSpec(std::set<RTLIL::SigBit> bits); + SigSpec(RTLIL::SigSpec &&other) { + width_ = other.width_; + hash_ = other.hash_; + chunks_.swap(other.chunks_); + bits_.swap(other.bits_); + } + + const RTLIL::SigSpec &operator=(RTLIL::SigSpec &&other) { + width_ = other.width_; + hash_ = other.hash_; + chunks_.swap(other.chunks_); + bits_.swap(other.bits_); + return *this; + } + inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; } inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; } |