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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:40:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 0bd8fafbd2f36f59327289e52abf962c166dab8b (patch) | |
| tree | f736d866783e2255bc18412c6bd330fd8c9f72ce /kernel | |
| parent | 10e5791c5e5660cb784503d36439ee90d61eb06b (diff) | |
| download | yosys-0bd8fafbd2f36f59327289e52abf962c166dab8b.tar.gz yosys-0bd8fafbd2f36f59327289e52abf962c166dab8b.tar.bz2 yosys-0bd8fafbd2f36f59327289e52abf962c166dab8b.zip | |
Added RTLIL::Design::modules()
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7249f0cad..6eb52cf2d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -340,6 +340,7 @@ struct RTLIL::Selection struct RTLIL::Design { + int refcount_modules_; std::map<RTLIL::IdString, RTLIL::Module*> modules_; std::vector<RTLIL::Selection> selection_stack; @@ -348,6 +349,8 @@ struct RTLIL::Design ~Design(); + RTLIL::ObjRange<RTLIL::Module*> modules() { return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_); } + void check(); void optimize(); |