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* Add "setundef -anyseq"Clifford Wolf2017-05-281-12/+12
* Enable readline and tcl in mxe buildsClifford Wolf2017-05-171-0/+10
* Add missing AndnotGate() and OrnotGate() declarations to rtlil.hClifford Wolf2017-05-171-13/+15
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-176-55/+94
* Add ConstEval defaultval featureClifford Wolf2017-04-051-1/+8
* Add front-end detection for *.tcl filesClifford Wolf2017-03-281-1/+6
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-253-1/+21
* Fix mingw compile issue (2nd attempt)Clifford Wolf2017-02-231-2/+2
* Fix mingw compile issue (maybe.. I can't test it)Clifford Wolf2017-02-231-2/+2
* Fix eval implementation of $_NOR_Clifford Wolf2017-02-161-1/+1
* Add "yosys -w" for suppressing warningsClifford Wolf2017-02-123-11/+34
* Add log_wire() APIClifford Wolf2017-02-112-0/+8
* Fix undef propagation bug in $pmux SAT modelClifford Wolf2017-02-051-14/+4
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-043-1/+11
* Fix RTLIL::Memory::start_offset initializationClifford Wolf2017-01-251-0/+1
* Bugfix in RTLIL::SigSpec::remove2()Clifford Wolf2016-12-311-3/+4
* Simplified log_spacer() codeClifford Wolf2016-12-231-6/+2
* Added "yosys -W regex"Clifford Wolf2016-12-223-2/+44
* Added AIGER back-end to automatic back-end detectionClifford Wolf2016-12-211-0/+2
* Bugfix in comment handlingClifford Wolf2016-12-131-1/+1
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-152-1/+4
* Some minor build fixes for Visual CClifford Wolf2016-10-142-1/+5
* Added $anyseq cell typeClifford Wolf2016-10-144-3/+19
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-1/+2
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-124-1/+31
* define PATH_MAX if not defined by limits.hClifford Wolf2016-10-111-0/+5
* Improvements in assertpmuxClifford Wolf2016-09-072-0/+19
* Removed $aconst cell typeClifford Wolf2016-08-302-2/+1
* Removed $predict againClifford Wolf2016-08-283-11/+1
* Fixed handling of transparent bram rd ports on ROMsClifford Wolf2016-08-271-0/+1
* Added glob support to all front-endsClifford Wolf2016-08-223-4/+38
* Add MSYS2-compatible build.William D. Jones2016-08-161-2/+1
* Use _Exit(0) on win32, always use _Exit(1) in log_error()Clifford Wolf2016-08-162-1/+6
* Added log_const() APIClifford Wolf2016-08-092-0/+19
* Use /proc/self/exe on Cygwin as well.Yury Gribov2016-08-081-1/+1
* Added SatGen support for $anyconstClifford Wolf2016-07-271-0/+22
* Removed $predict support from SatGenClifford Wolf2016-07-271-9/+0
* Added $anyconst and $aconstClifford Wolf2016-07-272-0/+8
* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-272-0/+8
* Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()Clifford Wolf2016-07-252-2/+2
* Improvements in CellEdgesDatabaseClifford Wolf2016-07-242-13/+134
* Added CellEdgesDatabase APIClifford Wolf2016-07-242-0/+151
* Added satgen initstate supportClifford Wolf2016-07-221-0/+27
* Added $initstate cell type and vlog functionClifford Wolf2016-07-213-3/+10
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-213-4/+4
* Added basic support for $expect cellsClifford Wolf2016-07-134-8/+29
* A few modifications after pull request commentsRuben Undheim2016-06-182-3/+2
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-182-0/+4
* Added $sop SAT modelClifford Wolf2016-06-171-0/+82
* Improved support for $sop cellsClifford Wolf2016-06-172-4/+16
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