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* coolrunner2: Initial techmapping for $sopRobert Ou2017-06-254-153/+268
* coolrunner2: Initial commitRobert Ou2017-06-243-0/+223
* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...Clifford Wolf2017-06-075-4/+61
* Fix handling of Verilog ~& and ~| operatorsClifford Wolf2017-06-011-0/+8
* Update ABC to hg rev efbf7f13ea9eClifford Wolf2017-05-311-1/+1
* Add dff2ff.v techmap fileClifford Wolf2017-05-312-0/+15
* Fix AIGER back-end for multiple symbols per input/latch/output/propertyClifford Wolf2017-05-301-8/+20
* Add "setundef -anyseq"Clifford Wolf2017-05-283-15/+56
* Improve write_aiger handling of unconnected nets and constantsClifford Wolf2017-05-282-8/+62
* Change default smt2 solver to yices (Yices 2 has switched its license to GPL)Clifford Wolf2017-05-271-4/+4
* Add aliases for common sets of gate types to "abc -g"Clifford Wolf2017-05-241-2/+74
* Add examples/osu035Clifford Wolf2017-05-234-0/+30
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-05-231-17/+70
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| * Merge pull request #346 from azonenberg/masterClifford Wolf2017-05-231-17/+70
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| | * greenpak4_counters: Added support for parallel output from GP_COUNTx cellsAndrew Zonenberg2017-05-221-17/+70
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* / Add workaround for CBMC bug to SimpleC back-endClifford Wolf2017-05-171-1/+3
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* Enable readline and tcl in mxe buildsClifford Wolf2017-05-173-4/+44
* Add missing AndnotGate() and OrnotGate() declarations to rtlil.hClifford Wolf2017-05-171-13/+15
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-1714-91/+211
* Add <modname>_init() function generator to simpleC back-endClifford Wolf2017-05-162-88/+152
* Improve simplec back-endClifford Wolf2017-05-161-1/+1
* Improve simplec back-endClifford Wolf2017-05-151-42/+44
* Improve simplec back-endClifford Wolf2017-05-143-3/+49
* Improve simplec back-endClifford Wolf2017-05-131-25/+60
* Improve simplec back-endClifford Wolf2017-05-123-12/+78
* Added support for more gate types to simplec back-endClifford Wolf2017-05-121-1/+88
* Add first draft of simple C back-endClifford Wolf2017-05-126-0/+623
* Update ABC to hg rev e79576e10d72Clifford Wolf2017-05-111-1/+1
* Fix boolector support in yosys-smtbmcClifford Wolf2017-05-081-18/+18
* Add support for localparam in module headerClifford Wolf2017-04-301-1/+7
* Fix equiv_simple, old behavior now available with "equiv_simple -short"Clifford Wolf2017-04-281-10/+41
* Add support for `resetall compiler directiveClifford Wolf2017-04-261-0/+7
* Replace CRLF line endings with LF in de2i.qsf (quartus example)Clifford Wolf2017-04-121-1098/+1098
* Squelch trailing whitespaceLarry Doolittle2017-04-1219-165/+165
* Add MAX10 and Cyclone IV items to CHANGELOGClifford Wolf2017-04-071-0/+13
* Merge pull request #337 from dh73/masterClifford Wolf2017-04-0725-0/+2255
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| * Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAsdh732017-04-0525-0/+2255
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* Add ConstEval defaultval featureClifford Wolf2017-04-051-1/+8
* Fix gcc compiler warningClifford Wolf2017-04-051-1/+1
* Add front-end detection for *.tcl filesClifford Wolf2017-03-281-1/+6
* Add minisat 00_PATCH_typofixes.patchClifford Wolf2017-03-272-0/+21
* Remove use of <fpu_control.h> in minisatClifford Wolf2017-03-274-18/+44
* Add "write_smt2 -stdt" modeClifford Wolf2017-03-202-37/+84
* Add generation of logic cells to EDIF back-end runtest.pyClifford Wolf2017-03-191-2/+6
* Fix EDIF: portRef member 0 is always the MSB bitClifford Wolf2017-03-192-13/+14
* Add simple EDIF test case generator and checkerClifford Wolf2017-03-181-0/+113
* Fix verilog pre-processor for multi-level relative includesClifford Wolf2017-03-141-4/+26
* Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msgClifford Wolf2017-03-042-33/+87
* Add write_aiger $anyseq supportClifford Wolf2017-03-021-0/+7
* Allow $anyconst, etc. in non-formal SV modeClifford Wolf2017-03-011-1/+1
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