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| author | Clifford Wolf <clifford@clifford.at> | 2016-11-15 12:42:43 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-11-15 12:42:43 +0100 |
| commit | a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51 (patch) | |
| tree | effa1745fb6b7c2320455c2d4f7c58171e8edab1 /kernel | |
| parent | a2206180d60c857578209300c3a693e9c4723459 (diff) | |
| download | yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.tar.gz yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.tar.bz2 yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.zip | |
Remember global declarations and defines accross read_verilog calls
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 | ||||
| -rw-r--r-- | kernel/rtlil.h | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 66bbf0427..7693e3052 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -306,6 +306,8 @@ RTLIL::Design::~Design() delete it->second; for (auto n : verilog_packages) delete n; + for (auto n : verilog_globals) + delete n; } RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules() diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9430dcb36..8dd8fcca3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -793,7 +793,8 @@ struct RTLIL::Design int refcount_modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_; - std::vector<AST::AstNode*> verilog_packages; + std::vector<AST::AstNode*> verilog_packages, verilog_globals; + dict<std::string, std::pair<std::string, bool>> verilog_defines; std::vector<RTLIL::Selection> selection_stack; dict<RTLIL::IdString, RTLIL::Selection> selection_vars; |