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* Merge pull request #3310 from robinsonb5-PRs/masterMiodrag Milanović2022-05-171-0/+2
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| * Use log_warning when Tcl_Init fails, report error with Tcl_ErrnoMsg.Alastair M. Robinson2022-05-161-1/+1
| * Now calls Tcl_Init after creating the interp, fixes clock format.Alastair M. Robinson2022-05-101-0/+2
* | Add opt_ffinv pass.Marcelina Kościelnicka2022-05-132-3/+12
* | Add proc_rom pass.Marcelina Kościelnicka2022-05-131-1/+1
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* Handle possible non-memory indexed dataMiodrag Milanovic2022-05-061-8/+10
* map memory location to wire value, if memory is converted to FFsMiodrag Milanovic2022-05-041-0/+4
* Start restoring memory state from VCD/FSTMiodrag Milanovic2022-05-042-1/+33
* Ignore change on last edgeMiodrag Milanovic2022-04-221-4/+5
* Proper scope naming from FSTMiodrag Milanovic2022-03-302-9/+4
* kernel/mem: Only use FF init in read-first emu for mem with initMarcelina Kościelnicka2022-03-281-1/+4
* Add some more reserve calls to RTLIL::ConstNotAFile2022-03-251-0/+5
* More verbose warningsMiodrag Milanovic2022-03-181-1/+2
* Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-162-0/+2
* VCD reader support by using external toolMiodrag Milanovic2022-02-282-0/+20
* Fix for last clock edge dataMiodrag Milanovic2022-02-251-0/+1
* Changed error messageMiodrag Milanovic2022-02-181-1/+1
* Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-162-109/+54
* Merge branch 'master' into clk2ff-better-namesClaire Xen2022-02-1140-673/+4431
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| * Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-072-0/+333
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| | * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+2
| | * bug fix and cleanupsMiodrag Milanovic2022-02-041-1/+1
| | * CleanupMiodrag Milanovic2022-01-311-1/+0
| | * Display simulation time dataMiodrag Milanovic2022-01-312-1/+23
| | * ignore not found private signalsMiodrag Milanovic2022-01-281-2/+1
| | * preserve VCD mangled namesMiodrag Milanovic2022-01-281-1/+3
| | * detect edges even when xMiodrag Milanovic2022-01-281-2/+2
| | * cleanupMiodrag Milanovic2022-01-282-14/+1
| | * Do actual compareMiodrag Milanovic2022-01-282-72/+47
| | * Add more options and time handlingMiodrag Milanovic2022-01-282-0/+3
| | * Fix tabs/spacesMiodrag Milanovic2022-01-261-31/+31
| | * Add fstdata helper classMiodrag Milanovic2022-01-262-0/+344
| * | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-288-20/+291
| * | kernel/mem: Add read-first semantic emulation code.Marcelina Kościelnicka2022-01-282-0/+116
| * | kernel/mem: Add functions to emulate read port enable/init/reset signals.Marcelina Kościelnicka2022-01-272-0/+226
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| * logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-11/+11
| * Merge pull request #3111 from whitequark/issue-3110Catherine2021-12-141-1/+2
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| | * Fix null pointer dereference after failing to extract DFF from memory.Catherine2021-12-141-1/+2
| * | Hotfix for run_shell auto-detectionClaire Xenia Wolf2021-12-141-0/+3
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| * Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
| * Added "yosys -r <topmodule>"Claire Xenia Wolf2021-12-103-28/+35
| * Use "read" command to parse HDL files from Yosys command-lineClaire Xenia Wolf2021-12-091-4/+8
| * sta: very crude static timing analysis passLofty2021-11-254-17/+64
| * Make it work on allMiodrag Milanovic2021-11-051-3/+1
| * Removed semicolon from macroMiodrag Milanovic2021-11-051-1/+1
| * dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-272-7/+202
| * verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-253-0/+7
| * Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-3/+3
| * Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-2/+2
| * Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-1/+1
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