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* Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-211-0/+1
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| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-0/+1
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| | * Add a few more filename rewritesBen Widawsky2019-06-201-0/+1
| * | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-202-1/+32
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* | | Merge remote-tracking branch 'origin/eddie/fix1115' into xc7muxEddie Hung2019-06-201-1/+1
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| * | | Revert "Fix sign extension when sign is 1'bx"Eddie Hung2019-06-201-1/+1
* | | | Merge remote-tracking branch 'origin/eddie/fix1115' into xc7muxEddie Hung2019-06-201-1/+1
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| * | | Fix sign extension when sign is 1'bxEddie Hung2019-06-201-1/+1
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-202-1/+32
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| * | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-191-0/+4
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| | * | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
| * | | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* | / Remove iterator based Module::remove as per @cliffordwolfEddie Hung2019-06-182-11/+3
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* | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-172-2/+11
* | Further cleanup based on @daveshah1Eddie Hung2019-06-141-0/+6
* | Move ConstEvalAig to aigerparse.ccEddie Hung2019-06-131-157/+0
* | More slimmingEddie Hung2019-06-131-35/+35
* | Add ConstEvalAig specialised for AIGsEddie Hung2019-06-131-0/+157
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-129-21/+187
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| * Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-4/+4
| * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-072-0/+12
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| | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+12
| * | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-0/+1
| * | Fix handling of warning and error messages within log_make_debug-blocksClifford Wolf2019-05-221-0/+9
| * | Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-152-7/+82
| * | Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-0/+3
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| | * | Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-0/+3
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| * | Merge pull request #998 from mdaiter/get_bool_attribute_optsClifford Wolf2019-05-081-4/+8
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| | * | Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
| * | | Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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| * | Improve write_verilog specify supportClifford Wolf2019-05-041-1/+1
| * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-034-3/+18
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| | * Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | * fix codestyle formattingOleg Endo2019-04-293-14/+14
| | * escape spaces with backslash when writing dep fileOleg Endo2019-04-293-2/+17
| * | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| * | Improve $specrule interfaceClifford Wolf2019-04-231-1/+2
| * | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-0/+17
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
| * | Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-231-0/+3
| * | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| * | Add specify parserClifford Wolf2019-04-231-0/+10
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| * Fixes for OAI4 cell implementationDavid Shah2019-04-232-2/+2
* | Remove kernel/cost.cc since master has refactored itEddie Hung2019-04-221-75/+0
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-229-5/+289
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| * Add log_debug() frameworkClifford Wolf2019-04-224-1/+58
| * Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-226-4/+184
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| | * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
| | * Added support for changing Yosys namespaceBenedikt Tutzer2019-04-031-0/+1
| | * Fixed identationBenedikt Tutzer2019-04-011-1/+1