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* Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-152-7/+82
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-0/+3
|\ | | | | Fix all warnings that occurred when compiling with gcc9
| * Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-0/+3
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* | Merge pull request #998 from mdaiter/get_bool_attribute_optsClifford Wolf2019-05-081-4/+8
|\ \ | | | | | | Minor optimization to get_attribute_bool
| * | Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
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* | | Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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* | Improve write_verilog specify supportClifford Wolf2019-05-041-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-034-3/+18
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| * Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * fix codestyle formattingOleg Endo2019-04-293-14/+14
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| * escape spaces with backslash when writing dep fileOleg Endo2019-04-293-2/+17
| | | | | | | | | | | | filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames.
* | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-0/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-231-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add specify parserClifford Wolf2019-04-231-0/+10
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes for OAI4 cell implementationDavid Shah2019-04-232-2/+2
| | | | | | Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah <dave@ds0.me>
* Add log_debug() frameworkClifford Wolf2019-04-224-1/+58
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-226-4/+184
|\ | | | | Feature/python bindings
| * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
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| * Added support for changing Yosys namespaceBenedikt Tutzer2019-04-031-0/+1
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| * Fixed identationBenedikt Tutzer2019-04-011-1/+1
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| * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-2815-127/+297
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| * | Exposed generator script to make-processBenedikt Tutzer2018-09-192-3888/+2
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| * | added functions whose definitions are split over multiple linesBenedikt Tutzer2018-08-231-0/+60
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| * | added default yosys license textBenedikt Tutzer2018-08-231-0/+19
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| * | Fixed segfault / multiple free issue with listsBenedikt Tutzer2018-08-231-26/+38
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| * | Do not pass heap object to Python. This way they should be completely ↵Benedikt Tutzer2018-08-221-323/+337
| | | | | | | | | | | | managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function
| * | Fixed IdentationBenedikt Tutzer2018-08-221-189/+188
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| * | Wrapped functions that use unsigned int or type_t as typesBenedikt Tutzer2018-08-211-7/+127
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| * | added operators <, == and !=Benedikt Tutzer2018-08-211-0/+45
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| * | Added previousely missed functionsBenedikt Tutzer2018-08-211-1/+445
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| * | Deleted duplicate DestructorBenedikt Tutzer2018-08-211-1/+0
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| * | added some checks if python is enabled to make sure everything compiles if ↵Benedikt Tutzer2018-08-204-7/+8
| | | | | | | | | | | | python is disabled in the makefile
| * | The share directory cannot be searched when used as a Python library, only ↵Benedikt Tutzer2018-08-202-1/+8
| | | | | | | | | | | | in shell mode
| * | Python passes are now looked for in share/plugins and can be added by ↵Benedikt Tutzer2018-08-201-4/+1
| | | | | | | | | | | | specifying a relative or absolute path
| * | Fixed issue when using a python plugin in the yosys shellBenedikt Tutzer2018-08-203-4/+28
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| * | Python Passes can now be added with the -m option or with the plugin ↵Benedikt Tutzer2018-08-163-1/+96
| | | | | | | | | | | | command. There are still issues when run in shell mode, but they can be used just fine in a python script
| * | Added Wrappers for:Benedikt Tutzer2018-08-133-142/+2923
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h
| * | Saving id and pointer to c++ object. Object is valid only if both id and ↵Benedikt Tutzer2018-08-011-8/+29
| | | | | | | | | | | | pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
| * | Setup is called automatically when the module is loaded, shutdown when ↵Benedikt Tutzer2018-08-011-16/+19
| | | | | | | | | | | | python exits
| * | Cleaned up commentsBenedikt Tutzer2018-08-011-9/+3
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| * | Added Monitor class that can monitor all changes in a Design or in a ModuleBenedikt Tutzer2018-07-101-0/+119
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| * | added destructors for wires and cellsBenedikt Tutzer2018-07-102-1/+16
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| * | removed debug outputBenedikt Tutzer2018-07-091-1/+0
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| * | commands can now be run on arbitrary designs, not only on the active oneBenedikt Tutzer2018-07-091-0/+10
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| * | multiple designs can now exist independent from each other. ↵Benedikt Tutzer2018-07-093-45/+118
| | | | | | | | | | | | Cells/Wires/Modules can now move to a different parent without referencing issues
| * | Introduced namespace and removed class-prefixes to increase readabilityBenedikt Tutzer2018-06-281-163/+165
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