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| author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-08-01 08:05:39 +0200 |
|---|---|---|
| committer | Benedikt Tutzer <benedikt_tutzer@yahoo.de> | 2018-08-01 10:57:41 +0200 |
| commit | 57d2197703da12750fb508736ccfaf59b847ea22 (patch) | |
| tree | 023cc02cb897f8971904d8e460caf8691f404699 /kernel | |
| parent | b57dafce6819516d529cc0077b95cb3293a5dc06 (diff) | |
| download | yosys-57d2197703da12750fb508736ccfaf59b847ea22.tar.gz yosys-57d2197703da12750fb508736ccfaf59b847ea22.tar.bz2 yosys-57d2197703da12750fb508736ccfaf59b847ea22.zip | |
Cleaned up comments
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/python_wrappers.cc | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 4ba2a1185..ba7be9106 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -194,19 +194,17 @@ namespace YOSYS_PYTHON { virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE { - //log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE { - //log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector<Yosys::RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE { - //log("#TRACE# New connections in module %s:\n", log_id(module)); - //for (auto &sigsig : sigsig_vec) - // log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE @@ -214,10 +212,6 @@ namespace YOSYS_PYTHON { py_notify_blackout(new Module(module)); } - //virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { } - //virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } - //virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { } - virtual void py_notify_module_add(Module*){}; virtual void py_notify_module_del(Module*){}; virtual void py_notify_blackout(Module*){}; |