iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08	1	-8/+17
*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07	1	-0/+2
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	3	-4/+54
*	Stronger checking of internal cells	Clifford Wolf	2014-02-07	1	-29/+37
*	Added echo command	Clifford Wolf	2014-02-07	3	-4/+47
*	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	2	-0/+19
*	Added support for #-comments in same line as command	Clifford Wolf	2014-02-06	1	-0/+2
*	Added support for backslash continuation in script files	Clifford Wolf	2014-02-06	1	-2/+13
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-7/+16
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+2
*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02	2	-0/+10
*	Added yosys -H for command list	Clifford Wolf	2014-01-30	1	-1/+7
*	Added -h command line option	Clifford Wolf	2014-01-29	1	-2/+8
*	Added $assert support to satgen	Clifford Wolf	2014-01-19	1	-0/+21
*	Added $assert cell	Clifford Wolf	2014-01-19	2	-0/+8
*	Some improvements in log_dump_val_worker() templates	Clifford Wolf	2014-01-17	1	-1/+6
*	Added select -assert-none and -assert-any	Clifford Wolf	2014-01-17	1	-0/+3
*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03	2	-10/+43
*	Added RTLIL::SigSpec::optimized() API	Clifford Wolf	2014-01-03	2	-0/+8
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+1
*	Added SAT undef model for $pmux and $safe_pmux	Clifford Wolf	2014-01-02	1	-4/+19
*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02	1	-5/+3
*	Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint	Clifford Wolf	2013-12-31	1	-4/+11
*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29	1	-11/+8
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	4	-1/+12
*	Fixed sat handling of $eqx and $nex with unequal port widths	Clifford Wolf	2013-12-27	1	-0/+2
*	Small cleanup in SatGen	Clifford Wolf	2013-12-27	1	-2/+0
*	Fixed sat handling of $eqx and $nex cells	Clifford Wolf	2013-12-27	1	-1/+12
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	3	-5/+21
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	2	-0/+31
*	Added log_dump() API	Clifford Wolf	2013-12-20	1	-0/+54
*	Added "sat" undef support and "sat -set-init" options	Clifford Wolf	2013-12-07	1	-13/+24
*	Fixed uninitialized const flags bug	Clifford Wolf	2013-12-07	1	-1/+1
*	Fixes and improvements in RTLIL::SigSpec::parse	Clifford Wolf	2013-12-07	1	-2/+12
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	2	-4/+3
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	2	-7/+39
*	Added Pass:call_newsel API	Clifford Wolf	2013-12-02	2	-0/+27
*	Added "history" command	Clifford Wolf	2013-12-02	1	-0/+18
*	Using RTLIL::id2cstr for prompt printing	Clifford Wolf	2013-11-29	1	-1/+1
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25	1	-73/+170
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25	1	-27/+122
*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25	1	-25/+172
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-0/+1
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	2	-8/+1
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	2	-2/+3
*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23	1	-0/+6
*	Some driver changes/fixes	Clifford Wolf	2013-11-22	1	-5/+5
*	Added more performance measurement infrastructure	Clifford Wolf	2013-11-22	1	-0/+41
*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22	1	-30/+13
*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22	2	-24/+119