iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added $assume cell type	Clifford Wolf	2015-02-26	1	-0/+30
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-1/+31
*	Added "equiv_simple -undef"	Clifford Wolf	2015-01-31	1	-0/+14
*	Various equiv_simple improvements	Clifford Wolf	2015-01-22	1	-0/+19
*	Fixed a few VS warnings	Clifford Wolf	2014-10-17	1	-1/+1
*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10	1	-1/+1
*	Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32	Clifford Wolf	2014-10-10	1	-52/+52
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-32/+32
*	satgen import sigbit api	Clifford Wolf	2014-10-03	1	-1/+17
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+5
*	Simplified $fa undef model	Clifford Wolf	2014-09-08	1	-14/+1
*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-0/+32
*	Added "$fa" cell type	Clifford Wolf	2014-09-08	1	-0/+49
*	Added $macc SAT model	Clifford Wolf	2014-09-06	1	-0/+71
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-3/+3
*	Using $pos models for $bu0	Clifford Wolf	2014-09-03	1	-1/+1
*	Fixes in $alu SAT- and eval-models	Clifford Wolf	2014-09-03	1	-4/+3
*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	1	-3/+4
*	Added SAT model for $alu cells	Clifford Wolf	2014-09-01	1	-2/+69
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-1/+50
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-7/+81
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-1/+1
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-9/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-85/+85
*	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	Clifford Wolf	2014-07-30	1	-36/+39
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-4/+14
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-4/+4
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-85/+85
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-85/+85
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-6/+4
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-7/+7
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-7/+7
*	Bugfix in satgen for cells with wider in- than outputs.	Clifford Wolf	2014-07-21	1	-1/+9
*	Added libs/minisat (copy of minisat git master)	Clifford Wolf	2014-03-12	1	-6/+1
*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06	1	-3/+2
*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06	1	-1/+1
*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26	1	-4/+4
*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23	1	-0/+1
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+21
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-7/+16
*	Added $assert support to satgen	Clifford Wolf	2014-01-19	1	-0/+21
*	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	Clifford Wolf	2014-01-03	1	-6/+37
*	Added SAT undef model for $pmux and $safe_pmux	Clifford Wolf	2014-01-02	1	-4/+19
*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02	1	-5/+3
*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29	1	-11/+8
*	Fixed sat handling of $eqx and $nex with unequal port widths	Clifford Wolf	2013-12-27	1	-0/+2
*	Small cleanup in SatGen	Clifford Wolf	2013-12-27	1	-2/+0
*	Fixed sat handling of $eqx and $nex cells	Clifford Wolf	2013-12-27	1	-1/+12
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-4/+16