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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+7
* Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
* sta: very crude static timing analysis passLofty2021-11-251-0/+3
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+1
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-2/+2
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+6
* Add additional check to SigSpecClaire Xenia Wolf2021-09-101-2/+2
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-1/+10
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-2/+14
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-0/+2
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-0/+3
* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-251-0/+10
* blackbox: Include whiteboxed modulesgatecat2021-03-171-1/+1
* Replace assert in get_reference with more useful error messageLofty2021-03-171-1/+2
* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-0/+21
* Remove a few functions that, in fact, did not exist in the first place.Marcelina Kościelnicka2021-03-061-2/+0
* int -> boolRobert Baruch2021-02-231-2/+2
* Adds is_wire to SigBit and SigChunkRobert Baruch2021-02-231-0/+3
* verilog: significant block scoping improvementsZachary Snow2021-01-311-0/+4
* kernel: make IdString::isPublic() const.whitequark2020-12-121-1/+1
* add IdString::isPublic()N. Engelhardt2020-09-031-0/+2
* Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-231-0/+20
* Merge pull request #2177 from boqwxp/dict-iterator-jumpwhitequark2020-06-211-0/+23
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| * hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_i...Alberto Gonzalez2020-06-191-0/+23
* | rtlil: Add `Design::select()` for selecting whole modules.Alberto Gonzalez2020-06-191-0/+7
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* RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-091-0/+2
* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+3
* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-081-0/+2
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| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-0/+2
* | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-1/+1
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| * | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-1/+1
* | | Merge pull request #2070 from hackfin/masterN. Engelhardt2020-06-041-6/+3
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| * | idict handling in wrapperMartin2020-05-191-6/+3
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* | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-291-0/+10
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| * | Add comments for mod/div semantics to rtlil.hXiretza2020-05-281-0/+4
| * | Add flooring division operatorXiretza2020-05-281-0/+3
| * | Add flooring modulo operatorXiretza2020-05-281-0/+3
* | | Merge pull request #2092 from whitequark/rtlil-no-space-controlclairexen2020-05-291-3/+5
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| * | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-291-3/+5
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* | Merge pull request #2088 from rswarbrick/count-atwhitequark2020-05-281-2/+8
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| * | Minor optimisation in Module::wire() and Module::cell()Rupert Swarbrick2020-05-261-2/+8
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* | Merge pull request #2086 from rswarbrick/sigbitwhitequark2020-05-281-2/+1
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| * | Use default copy constructor for RTLIL::SigBitRupert Swarbrick2020-05-261-2/+1
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* / Use c_str(), not str() for IdString/std::string == and != operatorsRupert Swarbrick2020-05-261-2/+2
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* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+2
* rtlil: add AttrObject::has_attribute.whitequark2020-04-161-0/+2
* rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-161-2/+9
* Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-091-1/+1
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