| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 1 | -0/+7 |
| * | Fix unused param warning with ENABLE_NDEBUG. | Marcelina Kościelnicka | 2021-12-12 | 1 | -1/+1 |
| * | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 1 | -0/+3 |
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 1 | -0/+1 |
| * | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 1 | -1/+1 |
| * | Change implicit conversions from bool to Sig* to explicit. | Marcelina Kościelnicka | 2021-10-21 | 1 | -2/+2 |
| * | Add $aldff and $aldffe: flip-flops with async load. | Marcelina Kościelnicka | 2021-10-02 | 1 | -0/+6 |
| * | Add additional check to SigSpec | Claire Xenia Wolf | 2021-09-10 | 1 | -2/+2 |
| * | Generate an RTLIL representation of bind constructs | Rupert Swarbrick | 2021-08-13 | 1 | -1/+10 |
| * | rtlil: Make Process handling more uniform with Cell and Wire. | Marcelina Kościelnicka | 2021-07-12 | 1 | -2/+14 |
| * | opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. | Marcelina Kościelnicka | 2021-06-09 | 1 | -0/+2 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | kernel/rtlil: Extract some helpers for checking memory cell types. | Marcelina Kościelnicka | 2021-05-22 | 1 | -0/+3 |
| * | rtlil: add const accessors for modules, wires, and cells | Zachary Snow | 2021-03-25 | 1 | -0/+10 |
| * | blackbox: Include whiteboxed modules | gatecat | 2021-03-17 | 1 | -1/+1 |
| * | Replace assert in get_reference with more useful error message | Lofty | 2021-03-17 | 1 | -1/+2 |
| * | Add support for memory writes in processes. | Marcelina Kościelnicka | 2021-03-08 | 1 | -0/+21 |
| * | Remove a few functions that, in fact, did not exist in the first place. | Marcelina Kościelnicka | 2021-03-06 | 1 | -2/+0 |
| * | int -> bool | Robert Baruch | 2021-02-23 | 1 | -2/+2 |
| * | Adds is_wire to SigBit and SigChunk | Robert Baruch | 2021-02-23 | 1 | -0/+3 |
| * | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 1 | -0/+4 |
| * | kernel: make IdString::isPublic() const. | whitequark | 2020-12-12 | 1 | -1/+1 |
| * | add IdString::isPublic() | N. Engelhardt | 2020-09-03 | 1 | -0/+2 |
| * | Add add* functions for the new FF types | Marcelina Kościelnicka | 2020-06-23 | 1 | -0/+20 |
| * | Merge pull request #2177 from boqwxp/dict-iterator-jump | whitequark | 2020-06-21 | 1 | -0/+23 |
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| | * | hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_i... | Alberto Gonzalez | 2020-06-19 | 1 | -0/+23 |
| * | | rtlil: Add `Design::select()` for selecting whole modules. | Alberto Gonzalez | 2020-06-19 | 1 | -0/+7 |
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| * | RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC. | whitequark | 2020-06-09 | 1 | -0/+2 |
| * | flatten: preserve original object names via hdlname attribute. | whitequark | 2020-06-08 | 1 | -0/+3 |
| * | Merge pull request #2105 from whitequark/split-flatten-off-techmap | clairexen | 2020-06-08 | 1 | -0/+2 |
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| | * | RTLIL: factor out RTLIL::Module::addMemory. NFC. | whitequark | 2020-06-04 | 1 | -0/+2 |
| * | | Merge pull request #2006 from jersey99/signed-in-rtlil-wire | whitequark | 2020-06-04 | 1 | -1/+1 |
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| | * | | Preserve 'signed'-ness of a verilog wire through RTLIL | Vamsi K Vytla | 2020-04-27 | 1 | -1/+1 |
| * | | | Merge pull request #2070 from hackfin/master | N. Engelhardt | 2020-06-04 | 1 | -6/+3 |
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| | * | | idict handling in wrapper | Martin | 2020-05-19 | 1 | -6/+3 |
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| * | | Merge pull request #1885 from Xiretza/mod-rem-cells | clairexen | 2020-05-29 | 1 | -0/+10 |
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| | * | | Add comments for mod/div semantics to rtlil.h | Xiretza | 2020-05-28 | 1 | -0/+4 |
| | * | | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -0/+3 |
| | * | | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -0/+3 |
| * | | | Merge pull request #2092 from whitequark/rtlil-no-space-control | clairexen | 2020-05-29 | 1 | -3/+5 |
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| | * | | Restrict RTLIL::IdString to not contain whitespace or control chars. | whitequark | 2020-05-29 | 1 | -3/+5 |
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| * | | Merge pull request #2088 from rswarbrick/count-at | whitequark | 2020-05-28 | 1 | -2/+8 |
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| | * | | Minor optimisation in Module::wire() and Module::cell() | Rupert Swarbrick | 2020-05-26 | 1 | -2/+8 |
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| * | | Merge pull request #2086 from rswarbrick/sigbit | whitequark | 2020-05-28 | 1 | -2/+1 |
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| | * | | Use default copy constructor for RTLIL::SigBit | Rupert Swarbrick | 2020-05-26 | 1 | -2/+1 |
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| * / | Use c_str(), not str() for IdString/std::string == and != operators | Rupert Swarbrick | 2020-05-26 | 1 | -2/+2 |
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| * | ilang, ast: Store parameter order and default value information. | Marcelina Kościelnicka | 2020-04-21 | 1 | -1/+2 |
| * | rtlil: add AttrObject::has_attribute. | whitequark | 2020-04-16 | 1 | -0/+2 |
| * | rtlil: add AttrObject::{get,set}_string_attribute. | whitequark | 2020-04-16 | 1 | -2/+9 |
| * | Merge pull request #1858 from YosysHQ/eddie/fix1856 | Eddie Hung | 2020-04-09 | 1 | -1/+1 |
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