iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08	1	-8/+17
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+18
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*	Stronger checking of internal cells	Clifford Wolf	2014-02-07	1	-29/+37
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*	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	1	-0/+18
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+2
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*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02	1	-0/+9
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*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+7
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*	Added RTLIL::SigSpec::optimized() API	Clifford Wolf	2014-01-03	1	-0/+7
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+1
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*	Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint	Clifford Wolf	2013-12-31	1	-4/+11
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-1/+1
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-1/+1
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*	Fixes and improvements in RTLIL::SigSpec::parse	Clifford Wolf	2013-12-07	1	-2/+12
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-5/+27
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-6/+0
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
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*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22	1	-30/+13
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*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22	1	-24/+85
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*	Added information on all internal cell types to internal checker	Clifford Wolf	2013-11-11	1	-0/+340
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*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09	1	-0/+14
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*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07	1	-1/+1
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*	Fixed type of sign extension in opt_const $eq/$ne handling	Clifford Wolf	2013-11-07	1	-0/+16
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*	Added eval -vloghammer_report mode	Clifford Wolf	2013-11-06	1	-0/+3
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*	Changed NEW_WIRE API to return the wire, not the signal	Clifford Wolf	2013-10-18	1	-1/+1
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*	Added RTLIL NEW_WIRE macro	Clifford Wolf	2013-10-18	1	-0/+9
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*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	1	-0/+89
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*	Added "eval" pass	Clifford Wolf	2013-06-19	1	-0/+85
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*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18	1	-2/+31
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*	Added "dump" command (part ilang backend)	Clifford Wolf	2013-06-02	1	-7/+7
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*	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29	1	-3/+10
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*	Create nice errors when calling RTLIL::Module::derive() of base class	Clifford Wolf	2013-03-26	1	-3/+3
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+1081