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author | Clifford Wolf <clifford@clifford.at> | 2013-12-28 11:54:40 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-12-28 12:02:14 +0100 |
commit | c69c416d28015e496045d1b4529c465fbaad42e2 (patch) | |
tree | f70da346eabfcd5abfeee100a2470a4b50bea2ee /kernel/rtlil.cc | |
parent | 7f717875999f18065a69934db2075fd1508d3a7d (diff) | |
download | yosys-c69c416d28015e496045d1b4529c465fbaad42e2.tar.gz yosys-c69c416d28015e496045d1b4529c465fbaad42e2.tar.bz2 yosys-c69c416d28015e496045d1b4529c465fbaad42e2.zip |
Added $bu0 cell (for easy correct $eq/$ne mapping)
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 47dc098a4..b8c9e21ac 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -370,7 +370,7 @@ namespace { void check() { - if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$neg") { + if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { param("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); port("\\Y", param("\\Y_WIDTH")); |