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rtlil.cc
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Author
Age
Files
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*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵
Clifford Wolf
2014-07-22
1
-1
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+1
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created interim RTLIL::SigSpec::chunks_rw()
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-44
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+44
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*
SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ↵
Clifford Wolf
2014-07-22
1
-149
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+149
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added accessor functions
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-193
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+193
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*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
1
-15
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+6
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*
Added module->remove(), module->addWire(), module->addCell(), cell->check()
Clifford Wolf
2014-07-21
1
-8
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+39
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*
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
Clifford Wolf
2014-07-20
1
-3
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+10
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*
Added function-like cell creation helpers
Clifford Wolf
2014-07-18
1
-73
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+103
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*
Fixed RTLIL::SigSpec::append_bit() for appending constants
Clifford Wolf
2014-07-17
1
-2
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+3
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*
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf
2014-07-16
1
-2
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+2
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*
Add support for cell arrays
Clifford Wolf
2014-06-07
1
-1
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+2
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*
Added support for dlatchsr cells
Clifford Wolf
2014-03-31
1
-1
/
+58
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*
Fixed typo in RTLIL::Module::addAdff()
Clifford Wolf
2014-03-17
1
-1
/
+1
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*
Fixed typo in RTLIL::Module::{addSshl,addSshr}
Clifford Wolf
2014-03-15
1
-2
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+2
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*
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
Clifford Wolf
2014-03-15
1
-1
/
+54
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*
Progress in Verific bindings
Clifford Wolf
2014-03-14
1
-1
/
+1
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*
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
Clifford Wolf
2014-03-14
1
-0
/
+42
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*
Merged OSX fixes from Siesh1oo with some modifications
Clifford Wolf
2014-03-13
1
-0
/
+1
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*
Fixed a typo in RTLIL::Module::addReduce...
Clifford Wolf
2014-03-10
1
-5
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+5
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*
Added RTLIL::Module::add... helper methods
Clifford Wolf
2014-03-10
1
-0
/
+236
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*
Improved checking of internal cell conventions
Clifford Wolf
2014-02-08
1
-8
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+17
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*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
1
-0
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+18
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*
Stronger checking of internal cells
Clifford Wolf
2014-02-07
1
-29
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+37
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*
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf
2014-02-06
1
-0
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+18
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*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
1
-0
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+2
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*
Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf
2014-02-02
1
-0
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+9
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*
Added $assert cell
Clifford Wolf
2014-01-19
1
-0
/
+7
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*
Added RTLIL::SigSpec::optimized() API
Clifford Wolf
2014-01-03
1
-0
/
+7
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*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
1
-0
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+1
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*
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
Clifford Wolf
2013-12-31
1
-4
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+11
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*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
1
-1
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+1
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*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
1
-1
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+1
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*
Fixes and improvements in RTLIL::SigSpec::parse
Clifford Wolf
2013-12-07
1
-2
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+12
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*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
1
-1
/
+1
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*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
1
-5
/
+27
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*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
1
-6
/
+0
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*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
1
-1
/
+1
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*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
1
-30
/
+13
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*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
1
-24
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+85
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*
Added information on all internal cell types to internal checker
Clifford Wolf
2013-11-11
1
-0
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+340
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*
Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf
2013-11-09
1
-0
/
+14
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*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
1
-1
/
+1
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*
Fixed type of sign extension in opt_const $eq/$ne handling
Clifford Wolf
2013-11-07
1
-0
/
+16
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*
Added eval -vloghammer_report mode
Clifford Wolf
2013-11-06
1
-0
/
+3
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Changed NEW_WIRE API to return the wire, not the signal
Clifford Wolf
2013-10-18
1
-1
/
+1
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*
Added RTLIL NEW_WIRE macro
Clifford Wolf
2013-10-18
1
-0
/
+9
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Added "design" command (-reset, -save, -load)
Clifford Wolf
2013-07-27
1
-0
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+89
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Added "eval" pass
Clifford Wolf
2013-06-19
1
-0
/
+85
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Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
Clifford Wolf
2013-06-18
1
-2
/
+31
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*
Added "dump" command (part ilang backend)
Clifford Wolf
2013-06-02
1
-7
/
+7
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