iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-1/+13
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-2/+1
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*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02	1	-0/+1
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01	1	-33/+29
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*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-3/+7
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*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-0/+61
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*	Added $alu cell type	Clifford Wolf	2014-08-30	1	-0/+14
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*	Fixed module->addPmux()	Clifford Wolf	2014-08-30	1	-1/+0
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*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24	1	-4/+7
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*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-8/+3
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-0/+4
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*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19	1	-53/+76
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*	Improved sig.remove2() performance	Clifford Wolf	2014-08-17	1	-2/+11
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*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-0/+22
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*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16	1	-5/+12
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-4/+4
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-0/+16
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*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14	1	-24/+53
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*	Added module->ports	Clifford Wolf	2014-08-14	1	-1/+9
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*	Refactoring of CellType class	Clifford Wolf	2014-08-14	1	-10/+6
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-4/+3
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-0/+30
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-10/+16
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-2/+2
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-14/+14
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	1	-2/+2
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	1	-2/+6
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-13/+23
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*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	1	-1/+3
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-82/+102
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*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	1	-94/+79
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-0/+83
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-4/+4
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-0/+5
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-1/+4
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-0/+2
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-60/+59
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*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	1	-0/+12
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*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-3/+36
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*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27	1	-9/+26
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*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	1	-0/+12
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-9/+9
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*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	1	-6/+23
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-12/+12
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-20/+20
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-1/+13
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-0/+40
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