iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05	1	-2/+10
*	Added $assume cell type	Clifford Wolf	2015-02-26	1	-0/+1
*	Added $meminit cell type	Clifford Wolf	2015-02-14	1	-0/+1
*	Added $equiv cell type	Clifford Wolf	2015-01-19	1	-0/+1
*	Added global yosys_celltypes	Clifford Wolf	2014-12-29	1	-40/+57
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28	1	-6/+6
*	Added functionality to dff2dffe pass	Clifford Wolf	2014-12-08	1	-0/+1
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08	1	-0/+4
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-6/+6
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+3
*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-0/+1
*	Added "$fa" cell type	Clifford Wolf	2014-09-08	1	-0/+1
*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-6/+5
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-3/+2
*	Added eval model for $lut cells	Clifford Wolf	2014-08-31	1	-0/+26
*	Added $alu cell type	Clifford Wolf	2014-08-30	1	-0/+2
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-2/+2
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-6/+43
*	Added CellTypes::cell_evaluable()	Clifford Wolf	2014-08-16	1	-31/+37
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-2/+1
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	Added module->ports	Clifford Wolf	2014-08-14	1	-1/+2
*	Refactoring of CellType class	Clifford Wolf	2014-08-14	1	-135/+105
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-2/+1
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-5/+5
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-1/+5
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-7/+7
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-4/+4
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	1	-0/+9
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	1	-1/+1
*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07	1	-0/+2
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-4/+15
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+1
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-0/+2
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-0/+4
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+14
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-1/+3
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23	1	-0/+3
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14	1	-2/+5
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	1	-0/+8
*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+4
*	Added additional functionality and cleanups in sigtools.h and celltypes.h	Clifford Wolf	2013-03-15	1	-0/+9
*	Added #ci and #co selection operators	Clifford Wolf	2013-03-14	1	-5/+15
*	Added $sr cell type to celltypes.h	Clifford Wolf	2013-03-14	1	-0/+1
*	Added library support to celltypes class and show pass	Clifford Wolf	2013-03-03	1	-4/+35
*	initial import	Clifford Wolf	2013-01-05	1	-0/+210