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| * | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
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| * | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
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| * | verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
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* | | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-205-18/+325
|\ \ \ | |/ / |/| | Enum support
| * | remove unnecessary blank lineJeff Wang2020-02-171-2/+1
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| * | add attributes for enumerated values in ilangJeff Wang2020-02-173-2/+76
| | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * | separate out enum_item/param implementation when they should be differentJeff Wang2020-02-171-7/+16
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| * | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6Jeff Wang2020-01-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop.
| * | fix enum in generate blocksJeff Wang2020-01-161-0/+20
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| * | allow enums to be declared at toplevel scopeJeff Wang2020-01-161-0/+7
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| * | lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
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| * | allow enum typedefsJeff Wang2020-01-161-1/+6
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| * | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-165-17/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
|\ \ \ | | | | | | | | Fix crash on wire declaration with delay
| * | | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | | | Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-034-94/+118
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-022-4/+6
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-022-93/+110
| |\ \ \ | | | | | | | | | | ast: Add support for $sformatf system function
| | * | | ast: Add support for $sformatf system functionDavid Shah2020-01-192-93/+110
| | | |/ | | |/| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
* | | | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-311-1/+2
|/ / / | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
|\ \ \ | |_|/ |/| | Add Verific support for OPER_REDUCE_NAND
| * | Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
| | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
|\ \ \ | | | | | | | | `verific` pass to print help message when command syntax error
| * \ \ Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-2711-229/+347
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| * | | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
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| * | | OopsEddie Hung2019-11-191-1/+1
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| * | | Print help message for verific passEddie Hung2019-11-191-9/+12
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* | | | Merge pull request #1654 from YosysHQ/eddie/sby_fix69Claire Wolf2020-01-301-0/+6
|\ \ \ \ | |_|_|/ |/| | | verific: unflatten struct ports
| * | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
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| * | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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* | | Add and use SigSpec::reverse()Eddie Hung2020-01-281-3/+3
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* | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-2/+4
| | | | | | | | | | | | Now done in read_aiger
* | | read_aiger: set abc9_box_seq attrEddie Hung2020-01-241-0/+1
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* | | read_aiger: also parse abc9_mergeabilityEddie Hung2020-01-222-2/+6
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* | | read_aiger: discard LUT inputs with nodeID == 0; not < 2Eddie Hung2020-01-211-1/+1
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* | | read_aiger: ignore constant inputs on LUTsEddie Hung2020-01-211-3/+7
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* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-2/+2
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| * | read_aiger: $lut prefix in frontEddie Hung2020-01-151-2/+2
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* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-142-13/+17
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| * | read_aiger: also rename "$0"Eddie Hung2020-01-141-2/+2
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| * | read_aiger: uniquify wires with $aiger<autoidx> prefixEddie Hung2020-01-132-9/+13
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| * | read_aiger: make $and/$not/$lut the prefix not suffixEddie Hung2020-01-131-5/+5
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* | | abc9: break SCC by setting (* keep *) on output wiresEddie Hung2020-01-131-1/+3
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* | | read_aiger: more accurate debug messageEddie Hung2020-01-091-2/+4
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