iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge branch 'eddie/clkpart' into xaig_dff	Eddie Hung	2019-11-22	5	-18/+88
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\| *	Add Verific support for SVA nexttime properties	Clifford Wolf	2019-11-22	1	-0/+22
\| *	Improve handling of verific primitives in "verific -import -V" mode	Clifford Wolf	2019-11-22	1	-2/+2
\| *	Add Verific SVA support for "always" properties	Clifford Wolf	2019-11-22	1	-5/+15
\| *	sv: Correct parsing of always_comb, always_ff and always_latch	David Shah	2019-11-21	2	-5/+40
\| *	Correctly treat empty modules as blackboxes in Verific	Clifford Wolf	2019-11-20	1	-1/+1
\| *	Do not rename VHDL entities to "entity(impl)" when they are top modules	Clifford Wolf	2019-11-20	2	-5/+8
* \|	Consistent log message, ignore 's' extension	Eddie Hung	2019-11-20	1	-2/+3
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-11-19	9	-33/+260
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\| *	Add check for valid macro names in macro definitions	Clifford Wolf	2019-11-07	1	-7/+11
\| *	Improve naming scheme for (VHDL) modules imported from Verific	Clifford Wolf	2019-10-24	1	-3/+26
\| *	Add "verific -L"	Clifford Wolf	2019-10-24	1	-1/+12
\| *	Add "verilog_defines -list" and "verilog_defines -reset"	Clifford Wolf	2019-10-21	1	-0/+16
\| *	Fix handling of "restrict" in Verific front-end	Clifford Wolf	2019-10-21	1	-1/+1
\| *	Fix parsing of .cname BLIF statements	Clifford Wolf	2019-10-16	1	-1/+1
\| *	Add .blackbox support to blif front-end	Clifford Wolf	2019-10-16	1	-0/+6
\| *	Use "(id)" instead of "id" for types as temporary hack	Clifford Wolf	2019-10-14	5	-20/+187
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\| \| *	frontends/ast: code style	David Shah	2019-10-03	1	-2/+1
\| \| *	sv: Fix typedefs in blocks	David Shah	2019-10-03	1	-2/+2
\| \| *	sv: Disambiguate interface ports	David Shah	2019-10-03	1	-3/+19
\| \| *	sv: Fix memories of typedefs	David Shah	2019-10-03	1	-1/+1
\| \| *	sv: Add %expect	David Shah	2019-10-03	1	-0/+1
\| \| *	sv: Add support for memories of a typedef	David Shah	2019-10-03	1	-6/+20
\| \| *	sv: Add support for memory typedefs	David Shah	2019-10-03	2	-3/+34
\| \| *	sv: Fix typedefs in packages	David Shah	2019-10-03	1	-4/+10
\| \| *	sv: Fix typedef parameters	David Shah	2019-10-03	2	-6/+48
\| \| *	sv: Switch parser to glr, prep for typedef	David Shah	2019-10-03	5	-11/+89
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-10-08	1	-2/+6
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\| * \|	Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9	Eddie Hung	2019-10-08	1	-4/+4
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\| * \| \|	Fixes for MSVC build	Miodrag Milanovic	2019-10-04	1	-2/+6
* \| \| \|	Fix merge issues	Eddie Hung	2019-10-04	1	-1/+1
* \| \| \|	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	Eddie Hung	2019-10-04	1	-4/+4
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\| * \| \|	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-4/+4
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* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-10-03	3	-35/+61
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\| * \|	Merge pull request #1419 from YosysHQ/eddie/lazy_derive	Clifford Wolf	2019-10-03	2	-35/+59
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\| \| *	Fix for svinterfaces	Eddie Hung	2019-09-30	1	-2/+8
\| \| *	module->derive() to be lazy and not touch ast if already derived	Eddie Hung	2019-09-30	2	-33/+51
\| * \|	Define environ, fixes #1424	Miodrag Milanovic	2019-10-01	1	-0/+2
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* \|	Cleanup $currQ from aigerparse	Eddie Hung	2019-09-30	1	-2/+0
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-30	3	-2/+597
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\| *	Merge pull request #1406 from whitequark/connect_rpc	whitequark	2019-09-30	2	-0/+591
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\| \| *	rpc: new frontend.	whitequark	2019-09-30	2	-0/+591
\| * \|	Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in	Miodrag Milanović	2019-09-30	1	-2/+6
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\| \| * \|	Fix reading aig files on windows	Miodrag Milanovic	2019-09-29	1	-1/+5
\| \| * \|	Open aig frontend as binary file	Miodrag Milanovic	2019-09-29	1	-1/+1
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* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-29	1	-2/+2
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\| * \|	Force $inout.out ports to begin with '$' to indicate internal	Eddie Hung	2019-09-23	1	-2/+2
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* \|	Big rework; flop info now mostly in cells_sim.v	Eddie Hung	2019-09-28	1	-6/+13
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-27	5	-35/+73
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\| *	Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #...	Clifford Wolf	2019-09-20	2	-18/+30