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* Add additional help infoMiodrag Milanovic2022-10-311-0/+2
* Enable importing blackbox modules onlyMiodrag Milanovic2022-10-311-1/+33
* Support for reading liberty files using verificMiodrag Milanovic2022-10-311-1/+45
* Skip verific primitives and operators import by defaultMiodrag Milanovic2022-10-141-0/+1
* Add option to import all cells from all librariesMiodrag Milanovic2022-10-141-1/+30
* fix whitespaceMiodrag Milanovic2022-10-101-1/+1
* Merge pull request #3452 from ALGCDG/masterMiodrag Milanović2022-10-101-1/+8
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| * Changing error reason string to be based on lut input plane limit constant.Archie2022-10-021-1/+1
| * Adding check for BLIF names command input plane size.Archie2022-08-211-1/+8
* | Fix handling of verific -L options, add implicit "-L work"Claire Xenia Wolf2022-10-101-0/+14
* | Add support for EDIF file reading using VerificMiodrag Milanovic2022-10-041-1/+47
* | support file content redirection for verific frontenedMiodrag Milanovic2022-09-281-14/+60
* | Add comment for future selfMiodrag Milanovic2022-09-281-0/+7
* | Handle attributes imported from verificMiodrag Milanovic2022-09-281-5/+24
* | Import memory attributesMiodrag Milanovic2022-09-211-0/+1
* | verific: better fix for read callbackMiodrag Milanovic2022-09-071-5/+3
* | verific: fix crash when using prep right after readMiodrag Milanovic2022-09-071-0/+3
* | Fitting help messages to 80 character widthKrystalDelusion2022-08-241-6/+6
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* set default_nettype to wire for resetallMiodrag Milanovic2022-08-101-0/+1
* resetall does not affect text defines, but undefineall doesMiodrag Milanovic2022-08-101-0/+4
* Encode filename unprintable charsMiodrag Milanovic2022-08-083-27/+27
* verific - make filepath handling compatible with verilog frontendMiodrag Milanovic2022-08-081-15/+29
* Merge pull request #3089 from YosysHQ/gatecat/liberty_wbMiodrag Milanović2022-08-011-0/+14
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| * Add read_liberty -wbgatecat2021-11-251-0/+14
* | Setting wire upto in verific importMiodrag Milanovic2022-07-291-2/+5
* | Update READMEMiodrag Milanović2022-07-281-1/+1
* | Upadte documentation and changelogMiodrag Milanovic2022-07-041-0/+1
* | Update to new verific extensions intefaceMiodrag Milanovic2022-06-301-3/+29
* | Add check for BLIF with no model nameArchie2022-06-221-1/+4
* | Revert "use new verific extensions library"Miodrag Milanovic2022-06-211-70/+54
* | use new verific extensions libraryMiodrag Milanovic2022-06-171-54/+70
* | removed deprecated features codeMiodrag Milanovic2022-06-131-235/+0
* | verific: Added "-vlog-libext" option to specify search extension for librariesMiodrag Milanovic2022-06-091-1/+16
* | verific: proper file location for readmem commandsMiodrag Milanovic2022-06-041-0/+33
* | verilog: fix width/sign detection for functionsZachary Snow2022-05-301-5/+7
* | verilog: fix size and signedness of array querying functionsJannis Harder2022-05-302-3/+2
* | verilog: fix $past's signednessJannis Harder2022-05-252-1/+2
* | verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+1
* | fix text to fit 80 columnsMiodrag Milanovic2022-05-231-6/+9
* | Update verific command file documentationMiodrag Milanovic2022-05-231-17/+19
* | Use analysis mode if set in fileMiodrag Milanovic2022-05-231-2/+2
* | verific: Use new value change logic also for $stable of wide signals.Jannis Harder2022-05-111-7/+29
* | Merge pull request #3305 from jix/sva_value_change_logicJannis Harder2022-05-091-10/+25
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| * | verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-091-10/+25
* | | verific: Fix conditions of SVAs with explicit clocks within proceduresJannis Harder2022-05-033-5/+16
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* | Ignore merging past ffs that we are not properly mergingMiodrag Milanovic2022-04-291-0/+1
* | verific: allow memories to be inferred in loops (vhdl)Miodrag Milanovic2022-04-181-0/+1
* | verific: allow memories to be inferred in loopsN. Engelhardt2022-04-151-0/+1
* | sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-1/+11
* | Preserve internal wires for external netsMiodrag Milanovic2022-04-011-1/+1
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