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* | | Update verific.ccClaire Xen2021-12-101-4/+7
| | | | | | | | | Ad-hoc fixes/improvements
* | | If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
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* / Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
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* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* No need to alocate more memory than usedMiodrag Milanovic2021-11-101-1/+0
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* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Add "verific -cfg" commandClaire Xenia Wolf2021-11-011-2/+75
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
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* Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-271-4/+1
| | | | This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467.
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-41/+291
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-24/+57
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-251-1/+4
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* Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-202-11/+45
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* Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
|\ | | | | Add support for $aldff flip-flops to verific importer
| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
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* Specify minimum bison version 3.0+Zachary Snow2021-10-012-0/+4
| | | | | | | | | Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous release). Ideally, we would require "3" rather than "3.0" to give a better error message, but bison 2.3, which still ships with macOS, does not support major-only version requirements. With this change, building with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14: require bison 3.0, but have 2.3`.
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-241-0/+1
|\ | | | | Fix "make vgtest"
| * Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
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* | sv: support wand and wor of data typesZachary Snow2021-09-211-9/+12
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-4/+10
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
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* update required verific versionMiodrag Milanovic2021-09-021-1/+1
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* sv: support declaration in generate for initializationZachary Snow2021-08-311-1/+95
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* sv: support declaration in procedural for initializationZachary Snow2021-08-301-1/+48
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* Make Verific extensions optionalMiodrag Milanovic2021-08-201-1/+6
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* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-136-2/+193
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-121-11/+44
| | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846
* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
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* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
| | | | | | These are, by the standard, just aliases for wire/wand/wor. Fixes #2918.
* Require latest verificMiodrag Milanovic2021-08-021-1/+1
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* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+8
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* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-4/+31
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* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-284-51/+83
| | | | Fixes #2447.
* Update to latest verificMiodrag Milanovic2021-07-211-3/+3
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* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-165-4/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix two struct access bugsZachary Snow2021-07-153-1/+10
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-122-6/+2
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-091-14/+9
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* sv: fix a few struct and enum memory leaksZachary Snow2021-07-062-2/+11
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* Merge pull request #2835 from YosysHQ/verific_commandClaire Xen2021-07-051-0/+61
|\ | | | | Support command files in Verific
| * Add additional helpMiodrag Milanovic2021-07-051-0/+22
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| * Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
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