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* Merge pull request #2001 from whitequark/wasiwhitequark2020-05-011-1/+1
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| * Add WASI platform support.whitequark2020-04-301-1/+1
* | Merge pull request #1981 from YosysHQ/claire/fix1837Claire Wolf2020-05-011-0/+4
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| * Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
* | verific: ignore anonymous enumsEddie Hung2020-04-301-1/+4
* | verific: support VHDL enums tooEddie Hung2020-04-271-13/+43
* | verific: recover wiretype/enum attr as part of import_attributes()Eddie Hung2020-04-272-6/+35
* | Revert "verific: import enum attributes from verific"Eddie Hung2020-04-241-24/+0
* | verific: do not assert if wire not found; warn insteadEddie Hung2020-04-231-2/+6
* | verific: import enum attributes from verificEddie Hung2020-04-221-0/+20
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* ilang, ast: Store parameter order and default value information.Marcelina Koƛcielnicka2020-04-213-5/+13
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-214-15/+207
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| * Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| * Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
* | Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-212-0/+5
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| * | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-182-0/+5
* | | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
* | | Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
* | | Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` no...Alberto Gonzalez2020-04-171-0/+2
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* | Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-162-2/+7
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* Merge pull request #1918 from whitequark/simplify-improve_enumwhitequark2020-04-151-5/+3
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| * ast/simplify: improve enum handling.whitequark2020-04-151-5/+3
* | Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
* | Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-142-1/+25
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| * | support using previously declared types/localparams/params in packageJeff Wang2020-04-072-1/+25
* | | Merge pull request #1880 from jjj11x/duplicate_enumwhitequark2020-04-141-2/+3
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| * | duplicated enum item names should result in an errorJeff Wang2020-04-071-2/+3
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* | Merge pull request #1910 from boqwxp/cleanup_ilang_parserwhitequark2020-04-131-4/+4
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| * | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.Alberto Gonzalez2020-04-131-4/+4
* | | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
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* | Merge pull request #1875 from whitequark/read_ilang-int_overflowwhitequark2020-04-092-2/+14
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| * | read_ilang: improve style. NFC.whitequark2020-04-061-2/+1
| * | read_ilang: improve error message for overly long wires.whitequark2020-04-061-0/+3
| * | read_ilang: detect overflow of integer literals.whitequark2020-04-061-1/+11
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* / aigerparse: only define __STDC_FORMAT_MACROS it not already before.Henner Zeller2020-04-071-0/+2
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* Merge pull request #1853 from YosysHQ/eddie/fix_dynsliceEddie Hung2020-04-021-1/+2
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| * ast: cap dynamic range select to size of signal, suppresses warningsEddie Hung2020-04-011-1/+2
* | Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-029-449/+437
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-028-313/+301
| * | kernel: use more ID::*Eddie Hung2020-04-029-142/+142
* | | Merge pull request #1846 from dh73/ast_feClaire Wolf2020-04-021-0/+3
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| * | Replacing log_error for log_file_error due consistencyDiego H2020-03-311-2/+1
| * | Adding error message for when size (width) of number literal is zeroDiego H2020-03-301-0/+4
* | | Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-023-38/+44
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| * | | kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-38/+44
* | | | Merge pull request #1844 from YosysHQ/dave/gen-source-locDavid Shah2020-04-011-0/+6
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| * | | | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
* | | | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
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