Merge pull request #1767 from YosysHQ/eddie/idstrings

IdString: use more ID::*, make them easier to use, speed up IdString::in()

9 files changed, 437 insertions, 449 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 50c2a3ce6..cbce0c990 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -117,7 +117,7 @@ struct ConstEvalAig
 		sig2deps[output].insert(output);
 
 		RTLIL::Cell *cell = sig2driver.at(output);
-		RTLIL::SigBit sig_a = cell->getPort("\\A");
+		RTLIL::SigBit sig_a = cell->getPort(ID::A);
 		sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
 											   // that may occur does so here, and
 											   // not mid insertion (below)
@@ -125,8 +125,8 @@ struct ConstEvalAig
 		if (!inputs.count(sig_a))
 			compute_deps(sig_a, inputs);
 
-		if (cell->type == "$_AND_") {
-			RTLIL::SigSpec sig_b = cell->getPort("\\B");
+		if (cell->type == ID($_AND_)) {
+			RTLIL::SigSpec sig_b = cell->getPort(ID::B);
 			sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
 												   // that may occur does so here, and
 												   // not mid insertion (below)
@@ -135,34 +135,34 @@ struct ConstEvalAig
 			if (!inputs.count(sig_b))
 				compute_deps(sig_b, inputs);
 		}
-		else if (cell->type == "$_NOT_") {
+		else if (cell->type == ID($_NOT_)) {
 		}
 		else log_abort();
 	}
 
 	bool eval(RTLIL::Cell *cell)
 	{
-		RTLIL::SigBit sig_y = cell->getPort("\\Y");
+		RTLIL::SigBit sig_y = cell->getPort(ID::Y);
 		if (values_map.count(sig_y))
 			return true;
 
-		RTLIL::SigBit sig_a = cell->getPort("\\A");
+		RTLIL::SigBit sig_a = cell->getPort(ID::A);
 		if (!eval(sig_a))
 			return false;
 
 		RTLIL::State eval_ret = RTLIL::Sx;
-		if (cell->type == "$_NOT_") {
+		if (cell->type == ID($_NOT_)) {
 			if (sig_a == State::S0) eval_ret = State::S1;
 			else if (sig_a == State::S1) eval_ret = State::S0;
 		}
-		else if (cell->type == "$_AND_") {
+		else if (cell->type == ID($_AND_)) {
 			if (sig_a == State::S0) {
 				eval_ret = State::S0;
 				goto eval_end;
 			}
 
 			{
-				RTLIL::SigBit sig_b = cell->getPort("\\B");
+				RTLIL::SigBit sig_b = cell->getPort(ID::B);
 				if (!eval(sig_b))
 					return false;
 				if (sig_b == State::S0) {
@@ -478,9 +478,9 @@ void AigerReader::parse_xaiger()
 				log_assert(boxUniqueId > 0);
 				uint32_t oldBoxNum = parse_xaiger_literal(f);
 				RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
-				cell->setPort("\\i", SigSpec(State::S0, boxInputs));
-				cell->setPort("\\o", SigSpec(State::S0, boxOutputs));
-				cell->attributes["\\abc9_box_seq"] = oldBoxNum;
+				cell->setPort(ID(i), SigSpec(State::S0, boxInputs));
+				cell->setPort(ID(o), SigSpec(State::S0, boxOutputs));
+				cell->attributes[ID::abc9_box_seq] = oldBoxNum;
 				boxes.emplace_back(cell);
 			}
 		}
@@ -548,18 +548,18 @@ void AigerReader::parse_aiger_ascii()
 				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
 			if (l3 == 0)
-				q_wire->attributes["\\init"] = State::S0;
+				q_wire->attributes[ID::init] = State::S0;
 			else if (l3 == 1)
-				q_wire->attributes["\\init"] = State::S1;
+				q_wire->attributes[ID::init] = State::S1;
 			else if (l3 == l1) {
-				//q_wire->attributes["\\init"] = RTLIL::Sx;
+				//q_wire->attributes[ID::init] = RTLIL::Sx;
 			}
 			else
 				log_error("Line %u has invalid reset literal for latch!\n", line_count);
 		}
 		else {
 			// AIGER latches are assumed to be initialized to zero
-			q_wire->attributes["\\init"] = State::S0;
+			q_wire->attributes[ID::init] = State::S0;
 		}
 		latches.push_back(q_wire);
 	}
@@ -673,18 +673,18 @@ void AigerReader::parse_aiger_binary()
 				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
 			if (l3 == 0)
-				q_wire->attributes["\\init"] = State::S0;
+				q_wire->attributes[ID::init] = State::S0;
 			else if (l3 == 1)
-				q_wire->attributes["\\init"] = State::S1;
+				q_wire->attributes[ID::init] = State::S1;
 			else if (l3 == l1) {
-				//q_wire->attributes["\\init"] = RTLIL::Sx;
+				//q_wire->attributes[ID::init] = RTLIL::Sx;
 			}
 			else
 				log_error("Line %u has invalid reset literal for latch!\n", line_count);
 		}
 		else {
 			// AIGER latches are assumed to be initialized to zero
-			q_wire->attributes["\\init"] = State::S0;
+			q_wire->attributes[ID::init] = State::S0;
 		}
 		latches.push_back(q_wire);
 	}
@@ -747,7 +747,7 @@ void AigerReader::post_process()
 {
 	unsigned ci_count = 0, co_count = 0;
 	for (auto cell : boxes) {
-		for (auto &bit : cell->connections_.at("\\i")) {
+		for (auto &bit : cell->connections_.at(ID(i))) {
 			log_assert(bit == State::S0);
 			log_assert(co_count < outputs.size());
 			bit = outputs[co_count++];
@@ -755,7 +755,7 @@ void AigerReader::post_process()
 			log_assert(bit.wire->port_output);
 			bit.wire->port_output = false;
 		}
-		for (auto &bit : cell->connections_.at("\\o")) {
+		for (auto &bit : cell->connections_.at(ID(o))) {
 			log_assert(bit == State::S0);
 			log_assert((piNum + ci_count) < inputs.size());
 			bit = inputs[piNum + ci_count++];
@@ -776,10 +776,10 @@ void AigerReader::post_process()
 		log_assert(q->port_input);
 		q->port_input = false;
 
-		auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
-		ff->setPort("\\D", d);
-		ff->setPort("\\Q", q);
-		ff->attributes["\\abc9_mergeability"] = mergeability[i];
+		auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
+		ff->setPort(ID::D, d);
+		ff->setPort(ID::Q, q);
+		ff->attributes[ID::abc9_mergeability] = mergeability[i];
 	}
 
 	dict<RTLIL::IdString, int> wideports_cache;
@@ -866,7 +866,7 @@ void AigerReader::post_process()
 				int init;
 				mf >> init;
 				if (init < 2)
-					wire->attributes["\\init"] = init;
+					wire->attributes[ID::init] = init;
 			}
 			else if (type == "box") {
 				RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
@@ -929,8 +929,8 @@ void AigerReader::post_process()
 	design->add(module);
 
 	for (auto cell : module->cells().to_vector()) {
-		if (cell->type != "$lut") continue;
-		auto y_port = cell->getPort("\\Y").as_bit();
+		if (cell->type != ID($lut)) continue;
+		auto y_port = cell->getPort(ID::Y).as_bit();
 		if (y_port.wire->width == 1)
 			module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
 		else
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 2c1fc25ce..2b6002548 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -952,9 +952,9 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 	current_module = new AstModule;
 	current_module->ast = NULL;
 	current_module->name = ast->str;
-	current_module->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
+	current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
 		ast->location.first_column, ast->location.last_line, ast->location.last_column);
-	current_module->set_bool_attribute("\\cells_not_processed");
+	current_module->set_bool_attribute(ID::cells_not_processed);
 
 	current_ast_mod = ast;
 	AstNode *ast_before_simplify;
@@ -1007,61 +1007,61 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 			log("--- END OF AST DUMP ---\n");
 		}
 
-		if (flag_nowb && ast->attributes.count("\\whitebox")) {
-			delete ast->attributes.at("\\whitebox");
-			ast->attributes.erase("\\whitebox");
+		if (flag_nowb && ast->attributes.count(ID::whitebox)) {
+			delete ast->attributes.at(ID::whitebox);
+			ast->attributes.erase(ID::whitebox);
 		}
 
-		if (ast->attributes.count("\\lib_whitebox")) {
+		if (ast->attributes.count(ID::lib_whitebox)) {
 			if (!flag_lib || flag_nowb) {
-				delete ast->attributes.at("\\lib_whitebox");
-				ast->attributes.erase("\\lib_whitebox");
+				delete ast->attributes.at(ID::lib_whitebox);
+				ast->attributes.erase(ID::lib_whitebox);
 			} else {
-				if (ast->attributes.count("\\whitebox")) {
-					delete ast->attributes.at("\\whitebox");
-					ast->attributes.erase("\\whitebox");
+				if (ast->attributes.count(ID::whitebox)) {
+					delete ast->attributes.at(ID::whitebox);
+					ast->attributes.erase(ID::whitebox);
 				}
-				AstNode *n = ast->attributes.at("\\lib_whitebox");
-				ast->attributes["\\whitebox"] = n;
-				ast->attributes.erase("\\lib_whitebox");
+				AstNode *n = ast->attributes.at(ID::lib_whitebox);
+				ast->attributes[ID::whitebox] = n;
+				ast->attributes.erase(ID::lib_whitebox);
 			}
 		}
 
-		if (!blackbox_module && ast->attributes.count("\\blackbox")) {
-			AstNode *n = ast->attributes.at("\\blackbox");
+		if (!blackbox_module && ast->attributes.count(ID::blackbox)) {
+			AstNode *n = ast->attributes.at(ID::blackbox);
 			if (n->type != AST_CONSTANT)
 				log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n");
 			blackbox_module = n->asBool();
 		}
 
-		if (blackbox_module && ast->attributes.count("\\whitebox")) {
-			AstNode *n = ast->attributes.at("\\whitebox");
+		if (blackbox_module && ast->attributes.count(ID::whitebox)) {
+			AstNode *n = ast->attributes.at(ID::whitebox);
 			if (n->type != AST_CONSTANT)
 				log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n");
 			blackbox_module = !n->asBool();
 		}
 
-		if (ast->attributes.count("\\noblackbox")) {
+		if (ast->attributes.count(ID::noblackbox)) {
 			if (blackbox_module) {
-				AstNode *n = ast->attributes.at("\\noblackbox");
+				AstNode *n = ast->attributes.at(ID::noblackbox);
 				if (n->type != AST_CONSTANT)
 					log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n");
 				blackbox_module = !n->asBool();
 			}
-			delete ast->attributes.at("\\noblackbox");
-			ast->attributes.erase("\\noblackbox");
+			delete ast->attributes.at(ID::noblackbox);
+			ast->attributes.erase(ID::noblackbox);
 		}
 
 		if (blackbox_module)
 		{
-			if (ast->attributes.count("\\whitebox")) {
-				delete ast->attributes.at("\\whitebox");
-				ast->attributes.erase("\\whitebox");
+			if (ast->attributes.count(ID::whitebox)) {
+				delete ast->attributes.at(ID::whitebox);
+				ast->attributes.erase(ID::whitebox);
 			}
 
-			if (ast->attributes.count("\\lib_whitebox")) {
-				delete ast->attributes.at("\\lib_whitebox");
-				ast->attributes.erase("\\lib_whitebox");
+			if (ast->attributes.count(ID::lib_whitebox)) {
+				delete ast->attributes.at(ID::lib_whitebox);
+				ast->attributes.erase(ID::lib_whitebox);
 			}
 
 			std::vector<AstNode*> new_children;
@@ -1082,8 +1082,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 
 			ast->children.swap(new_children);
 
-			if (ast->attributes.count("\\blackbox") == 0) {
-				ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
+			if (ast->attributes.count(ID::blackbox) == 0) {
+				ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false);
 			}
 		}
 
@@ -1124,7 +1124,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 	}
 
 	if (ast->type == AST_INTERFACE)
-		current_module->set_bool_attribute("\\is_interface");
+		current_module->set_bool_attribute(ID::is_interface);
 	current_module->ast = ast_before_simplify;
 	current_module->nolatches = flag_nolatches;
 	current_module->nomeminit = flag_nomeminit;
@@ -1212,7 +1212,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 					continue;
 				} else {
 					log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n",
-							existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "",
+							existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",
 							(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column);
 					design->remove(existing_mod);
 				}
@@ -1385,12 +1385,12 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
 	std::string original_name = this->name.str();
 	std::string changed_name = original_name + "_before_replacing_local_interfaces";
 	design->rename(this, changed_name);
-	this->set_bool_attribute("\\to_delete");
+	this->set_bool_attribute(ID::to_delete);
 
 	// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
 	// new module.
-	if (this->get_bool_attribute("\\initial_top")) {
-		this->attributes.erase("\\initial_top");
+	if (this->get_bool_attribute(ID::initial_top)) {
+		this->attributes.erase(ID::initial_top);
 		is_top = true;
 	}
 
@@ -1400,10 +1400,10 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
 	design->add(newmod);
 	RTLIL::Module* mod = design->module(original_name);
 	if (is_top)
-		mod->set_bool_attribute("\\top");
+		mod->set_bool_attribute(ID::top);
 
 	// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
-	mod->set_bool_attribute("\\interfaces_replaced_in_module");
+	mod->set_bool_attribute(ID::interfaces_replaced_in_module);
 }
 
 // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
@@ -1473,7 +1473,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 				// We copy the cell of the interface to the sub-module such that it
 				//   can further be found if it is propagated down to sub-sub-modules etc.
 				RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name);
-				new_subcell->set_bool_attribute("\\is_interface");
+				new_subcell->set_bool_attribute(ID::is_interface);
 			}
 			else {
 				log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
@@ -1482,7 +1482,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 
 		// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
 		if (interfaces.size() > 0) {
-			mod->set_bool_attribute("\\interfaces_replaced_in_module");
+			mod->set_bool_attribute(ID::interfaces_replaced_in_module);
 		}
 
 	} else {
@@ -1496,7 +1496,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
 // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
 RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
 {
-	bool quiet = lib || attributes.count(ID(blackbox)) || attributes.count(ID(whitebox));
+	bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
 
 	AstNode *new_ast = NULL;
 	std::string modname = derive_common(design, parameters, &new_ast, quiet);
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 54d8a11fa..c0539252c 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -41,16 +41,14 @@ using namespace AST;
 using namespace AST_INTERNAL;
 
 // helper function for creating RTLIL code for unary operations
-static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
+static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
 {
-	std::stringstream sstr;
-	sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
-
-	RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
-	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+        IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+	RTLIL::Cell *cell = current_module->addCell(name, type);
+	cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
-	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+	wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	if (gen_attributes)
 		for (auto &attr : that->attributes) {
@@ -59,12 +57,12 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 			cell->attributes[attr.first] = attr.second->asAttrConst();
 		}
 
-	cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
-	cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
-	cell->setPort("\\A", arg);
+	cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
+	cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size());
+	cell->setPort(ID::A, arg);
 
-	cell->parameters["\\Y_WIDTH"] = result_width;
-	cell->setPort("\\Y", wire);
+	cell->parameters[ID::Y_WIDTH] = result_width;
+	cell->setPort(ID::Y, wire);
 	return wire;
 }
 
@@ -76,14 +74,12 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 		return;
 	}
 
-	std::stringstream sstr;
-	sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
-
-	RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
-	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+        IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
+	RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
+	cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
-	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+	wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	if (that != NULL)
 		for (auto &attr : that->attributes) {
@@ -92,26 +88,24 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 			cell->attributes[attr.first] = attr.second->asAttrConst();
 		}
 
-	cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
-	cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
-	cell->setPort("\\A", sig);
+	cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
+	cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
+	cell->setPort(ID::A, sig);
 
-	cell->parameters["\\Y_WIDTH"] = width;
-	cell->setPort("\\Y", wire);
+	cell->parameters[ID::Y_WIDTH] = width;
+	cell->setPort(ID::Y, wire);
 	sig = wire;
 }
 
 // helper function for creating RTLIL code for binary operations
-static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
+static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
-	std::stringstream sstr;
-	sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
-
-	RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
-	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+        IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+	RTLIL::Cell *cell = current_module->addCell(name, type);
+	cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
-	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+	wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
@@ -119,17 +113,17 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 		cell->attributes[attr.first] = attr.second->asAttrConst();
 	}
 
-	cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
-	cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
+	cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
+	cell->parameters[ID::B_SIGNED] = RTLIL::Const(that->children[1]->is_signed);
 
-	cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
-	cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
+	cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size());
+	cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size());
 
-	cell->setPort("\\A", left);
-	cell->setPort("\\B", right);
+	cell->setPort(ID::A, left);
+	cell->setPort(ID::B, right);
 
-	cell->parameters["\\Y_WIDTH"] = result_width;
-	cell->setPort("\\Y", wire);
+	cell->parameters[ID::Y_WIDTH] = result_width;
+	cell->setPort(ID::Y, wire);
 	return wire;
 }
 
@@ -141,11 +135,11 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 	std::stringstream sstr;
 	sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
 
-	RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
-	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+	RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
+	cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
-	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+	wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
@@ -153,12 +147,12 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 		cell->attributes[attr.first] = attr.second->asAttrConst();
 	}
 
-	cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
+	cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
 
-	cell->setPort("\\A", right);
-	cell->setPort("\\B", left);
-	cell->setPort("\\S", cond);
-	cell->setPort("\\Y", wire);
+	cell->setPort(ID::A, right);
+	cell->setPort(ID::B, left);
+	cell->setPort(ID::S, cond);
+	cell->setPort(ID::Y, wire);
 
 	return wire;
 }
@@ -199,7 +193,7 @@ struct AST_INTERNAL::ProcessGenerator
 	{
 		// generate process and simple root case
 		proc = new RTLIL::Process;
-		proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
+		proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
 		proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
 		for (auto &attr : always->attributes) {
 			if (attr.second->type != AST_CONSTANT)
@@ -221,7 +215,7 @@ struct AST_INTERNAL::ProcessGenerator
 		for (auto child : always->children)
 		{
 			if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
-					child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
+					child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) {
 				found_global_syncs = true;
 			}
 			if (child->type == AST_EDGE) {
@@ -245,7 +239,7 @@ struct AST_INTERNAL::ProcessGenerator
 		for (auto child : always->children)
 			if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
 				if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
-						child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
+						child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk))
 					continue;
 				found_clocked_sync = true;
 				if (found_global_syncs || found_anyedge_syncs)
@@ -267,7 +261,7 @@ struct AST_INTERNAL::ProcessGenerator
 		}
 
 		// create initial assignments for the temporary signals
-		if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
+		if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) {
 			subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
 		} else {
 			addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
@@ -335,7 +329,7 @@ struct AST_INTERNAL::ProcessGenerator
 			} while (current_module->wires_.count(wire_name) > 0);
 
 			RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
-			wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
+			wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
 
 			chunk.wire = wire;
 			chunk.offset = 0;
@@ -420,7 +414,7 @@ struct AST_INTERNAL::ProcessGenerator
 		for (auto &lvalue_c : lvalue.chunks()) {
 			RTLIL::SigSpec lhs = lvalue_c;
 			RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
-			if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
+			if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
 				rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
 			remove_unwanted_lvalue_bits(lhs, rhs);
 			actions.push_back(RTLIL::SigSig(lhs, rhs));
@@ -470,7 +464,7 @@ struct AST_INTERNAL::ProcessGenerator
 		case AST_CASE:
 			{
 				RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
-				sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
+				sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
 				sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
 				current_case->switches.push_back(sw);
 
@@ -504,7 +498,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 					RTLIL::CaseRule *backup_case = current_case;
 					current_case = new RTLIL::CaseRule;
-					current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
+					current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
 					last_generated_case = current_case;
 					addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
 					for (auto node : child->children) {
@@ -525,7 +519,7 @@ struct AST_INTERNAL::ProcessGenerator
 					subst_rvalue_map.restore();
 				}
 
-				if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
+				if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) {
 			#if 0
 					// this is a valid transformation, but as optimization it is premature.
 					// better: add a default case that assigns 'x' to everything, and let later
@@ -842,7 +836,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
 	// cases this variable is used to hold the type of the cell that should
 	// be instantiated for this type of AST node.
-	std::string type_name;
+	IdString type_name;
 
 	current_filename = filename;
 
@@ -873,19 +867,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		// This is used by the hierarchy pass to know when it can replace interface connection with the individual
 		// signals.
 		RTLIL::Wire *wire = current_module->addWire(str, 1);
-		wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+		wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 		wire->start_offset = 0;
 		wire->port_id = port_id;
 		wire->port_input = true;
 		wire->port_output = true;
-		wire->set_bool_attribute("\\is_interface");
+		wire->set_bool_attribute(ID::is_interface);
 		if (children.size() > 0) {
 			for(size_t i=0; i<children.size();i++) {
 				if(children[i]->type == AST_INTERFACEPORTTYPE) {
 					std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
-					wire->attributes["\\interface_type"] = res.first;
+					wire->attributes[ID::interface_type] = res.first;
 					if (res.second != "")
-						wire->attributes["\\interface_modport"] = res.second;
+						wire->attributes[ID::interface_modport] = res.second;
 					break;
 				}
 			}
@@ -910,8 +904,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
 			current_module->connect(wire, val);
 
-			wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
-			wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
+			wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+			wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
@@ -932,7 +926,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
 
 			RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
-			wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+			wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 			wire->start_offset = range_right;
 			wire->port_id = port_id;
 			wire->port_input = is_input;
@@ -945,8 +939,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				wire->attributes[attr.first] = attr.second->asAttrConst();
 			}
 
-			if (is_wand) wire->set_bool_attribute("\\wand");
-			if (is_wor)  wire->set_bool_attribute("\\wor");
+			if (is_wand) wire->set_bool_attribute(ID::wand);
+			if (is_wor)  wire->set_bool_attribute(ID::wor);
 		}
 		break;
 
@@ -963,7 +957,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
 
 			RTLIL::Memory *memory = new RTLIL::Memory;
-			memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+			memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 			memory->name = str;
 			memory->width = children[0]->range_left - children[0]->range_right + 1;
 			if (children[1]->range_right < children[1]->range_left) {
@@ -1018,7 +1012,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
 				RTLIL::Wire *wire = current_module->addWire(str);
-				wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+				wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 				wire->name = str;
 				if (flag_autowire)
 					log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
@@ -1033,7 +1027,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			}
 			else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
 				RTLIL::Wire *current_wire = current_module->wire(str);
-				if (current_wire->get_bool_attribute("\\is_interface"))
+				if (current_wire->get_bool_attribute(ID::is_interface))
 					is_interface = true;
 				// Ignore
 			}
@@ -1052,16 +1046,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
 			// with the individual signals:
 			if (is_interface) {
-				RTLIL::Wire *dummy_wire;
-				std::string dummy_wire_name = "$dummywireforinterface" + str;
-				if (current_module->wires_.count(dummy_wire_name))
-					dummy_wire = current_module->wires_[dummy_wire_name];
-				else {
+				IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str());
+				RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name);
+				if (!dummy_wire) {
 					dummy_wire = current_module->addWire(dummy_wire_name);
-					dummy_wire->set_bool_attribute("\\is_interface");
+					dummy_wire->set_bool_attribute(ID::is_interface);
 				}
-				RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
-				return tmp;
+				return dummy_wire;
 			}
 
 			wire = current_module->wires_[str];
@@ -1097,7 +1088,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					}
 					if (GetSize(shift_val) >= 32)
 						fake_ast->children[1]->is_signed = true;
-					RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
+					RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
 					delete left_at_zero_ast;
 					delete right_at_zero_ast;
 					delete fake_ast;
@@ -1181,9 +1172,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for unary operations: $not, $pos, $neg
-	if (0) { case AST_BIT_NOT: type_name = "$not"; }
-	if (0) { case AST_POS:     type_name = "$pos"; }
-	if (0) { case AST_NEG:     type_name = "$neg"; }
+	if (0) { case AST_BIT_NOT: type_name = ID($not); }
+	if (0) { case AST_POS:     type_name = ID($pos); }
+	if (0) { case AST_NEG:     type_name = ID($neg); }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
 			is_signed = children[0]->is_signed;
@@ -1196,10 +1187,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $and, $or, $xor, $xnor
-	if (0) { case AST_BIT_AND:  type_name = "$and"; }
-	if (0) { case AST_BIT_OR:   type_name = "$or"; }
-	if (0) { case AST_BIT_XOR:  type_name = "$xor"; }
-	if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
+	if (0) { case AST_BIT_AND:  type_name = ID($and); }
+	if (0) { case AST_BIT_OR:   type_name = ID($or); }
+	if (0) { case AST_BIT_XOR:  type_name = ID($xor); }
+	if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
@@ -1213,10 +1204,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
-	if (0) { case AST_REDUCE_AND:  type_name = "$reduce_and"; }
-	if (0) { case AST_REDUCE_OR:   type_name = "$reduce_or"; }
-	if (0) { case AST_REDUCE_XOR:  type_name = "$reduce_xor"; }
-	if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
+	if (0) { case AST_REDUCE_AND:  type_name = ID($reduce_and); }
+	if (0) { case AST_REDUCE_OR:   type_name = ID($reduce_or); }
+	if (0) { case AST_REDUCE_XOR:  type_name = ID($reduce_xor); }
+	if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
 			RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
@@ -1225,7 +1216,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 	// generate cells for unary operations: $reduce_bool
 	// (this is actually just an $reduce_or, but for clarity a different cell type is used)
-	if (0) { case AST_REDUCE_BOOL:  type_name = "$reduce_bool"; }
+	if (0) { case AST_REDUCE_BOOL:  type_name = ID($reduce_bool); }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
 			RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
@@ -1233,10 +1224,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $shl, $shr, $sshl, $sshr
-	if (0) { case AST_SHIFT_LEFT:   type_name = "$shl"; }
-	if (0) { case AST_SHIFT_RIGHT:  type_name = "$shr"; }
-	if (0) { case AST_SHIFT_SLEFT:  type_name = "$sshl"; }
-	if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
+	if (0) { case AST_SHIFT_LEFT:   type_name = ID($shl); }
+	if (0) { case AST_SHIFT_RIGHT:  type_name = ID($shr); }
+	if (0) { case AST_SHIFT_SLEFT:  type_name = ID($sshl); }
+	if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
@@ -1260,19 +1251,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			int width = width_hint > 0 ? width_hint : left.size();
 			is_signed = children[0]->is_signed;
 			if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
-				return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
-			return binop2rtlil(this, "$pow", width, left, right);
+				return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
+			return binop2rtlil(this, ID($pow), width, left, right);
 		}
 
 	// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
-	if (0) { case AST_LT:  type_name = "$lt"; }
-	if (0) { case AST_LE:  type_name = "$le"; }
-	if (0) { case AST_EQ:  type_name = "$eq"; }
-	if (0) { case AST_NE:  type_name = "$ne"; }
-	if (0) { case AST_EQX: type_name = "$eqx"; }
-	if (0) { case AST_NEX: type_name = "$nex"; }
-	if (0) { case AST_GE:  type_name = "$ge"; }
-	if (0) { case AST_GT:  type_name = "$gt"; }
+	if (0) { case AST_LT:  type_name = ID($lt); }
+	if (0) { case AST_LE:  type_name = ID($le); }
+	if (0) { case AST_EQ:  type_name = ID($eq); }
+	if (0) { case AST_NE:  type_name = ID($ne); }
+	if (0) { case AST_EQX: type_name = ID($eqx); }
+	if (0) { case AST_NEX: type_name = ID($nex); }
+	if (0) { case AST_GE:  type_name = ID($ge); }
+	if (0) { case AST_GT:  type_name = ID($gt); }
 		{
 			int width = max(width_hint, 1);
 			width_hint = -1, sign_hint = true;
@@ -1285,11 +1276,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $add, $sub, $mul, $div, $mod
-	if (0) { case AST_ADD: type_name = "$add"; }
-	if (0) { case AST_SUB: type_name = "$sub"; }
-	if (0) { case AST_MUL: type_name = "$mul"; }
-	if (0) { case AST_DIV: type_name = "$div"; }
-	if (0) { case AST_MOD: type_name = "$mod"; }
+	if (0) { case AST_ADD: type_name = ID($add); }
+	if (0) { case AST_SUB: type_name = ID($sub); }
+	if (0) { case AST_MUL: type_name = ID($mul); }
+	if (0) { case AST_DIV: type_name = ID($div); }
+	if (0) { case AST_MOD: type_name = ID($mod); }
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
@@ -1315,8 +1306,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for binary operations: $logic_and, $logic_or
-	if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
-	if (0) { case AST_LOGIC_OR:  type_name = "$logic_or"; }
+	if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
+	if (0) { case AST_LOGIC_OR:  type_name = ID($logic_or); }
 		{
 			RTLIL::SigSpec left = children[0]->genRTLIL();
 			RTLIL::SigSpec right = children[1]->genRTLIL();
@@ -1327,7 +1318,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_LOGIC_NOT:
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
-			return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
+			return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
 		}
 
 	// generate multiplexer for ternary operator (aka ?:-operator)
@@ -1353,7 +1344,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
 
 				if (cond.size() > 1)
-					cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
+					cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
 
 				int width = max(val1.size(), val2.size());
 				is_signed = children[1]->is_signed && children[2]->is_signed;
@@ -1374,11 +1365,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			std::stringstream sstr;
 			sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
 
-			RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
-			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
+			RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
+			cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
 
 			RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
-			wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
+			wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
 
 			int mem_width, mem_size, addr_bits;
 			is_signed = id2ast->is_signed;
@@ -1386,18 +1377,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
 
-			cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-			cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-			cell->setPort("\\ADDR", addr_sig);
-			cell->setPort("\\DATA", RTLIL::SigSpec(wire));
+			cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+			cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+			cell->setPort(ID::ADDR, addr_sig);
+			cell->setPort(ID::DATA, RTLIL::SigSpec(wire));
 
-			cell->parameters["\\MEMID"] = RTLIL::Const(str);
-			cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
-			cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
+			cell->parameters[ID::MEMID] = RTLIL::Const(str);
+			cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
+			cell->parameters[ID::WIDTH] = RTLIL::Const(wire->width);
 
-			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
-			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
-			cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+			cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
+			cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
+			cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
 
 			if (!sign_hint)
 				is_signed = false;
@@ -1412,8 +1403,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			std::stringstream sstr;
 			sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
 
-			RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
-			cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+			RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit));
+			cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 
 			int mem_width, mem_size, addr_bits;
 			id2ast->meminfo(mem_width, mem_size, addr_bits);
@@ -1423,26 +1414,26 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (children[2]->type != AST_CONSTANT)
 					log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
 				num_words = int(children[2]->asInt(false));
-				cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
+				cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
 			}
 
 			SigSpec addr_sig = children[0]->genRTLIL();
 
-			cell->setPort("\\ADDR", addr_sig);
-			cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
+			cell->setPort(ID::ADDR, addr_sig);
+			cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
 
-			cell->parameters["\\MEMID"] = RTLIL::Const(str);
-			cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
-			cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
+			cell->parameters[ID::MEMID] = RTLIL::Const(str);
+			cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
+			cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);
 
 			if (type == AST_MEMWR) {
-				cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-				cell->setPort("\\EN", children[2]->genRTLIL());
-				cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
-				cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
+				cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+				cell->setPort(ID::EN, children[2]->genRTLIL());
+				cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
+				cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
 			}
 
-			cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
+			cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
 		}
 		break;
 
@@ -1453,12 +1444,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_FAIR:
 	case AST_COVER:
 		{
-			const char *celltype = nullptr;
-			if (type == AST_ASSERT) celltype = "$assert";
-			if (type == AST_ASSUME) celltype = "$assume";
-			if (type == AST_LIVE) celltype = "$live";
-			if (type == AST_FAIR) celltype = "$fair";
-			if (type == AST_COVER) celltype = "$cover";
+			IdString celltype;
+			if (type == AST_ASSERT) celltype = ID($assert);
+			if (type == AST_ASSUME) celltype = ID($assume);
+			if (type == AST_LIVE) celltype = ID($live);
+			if (type == AST_FAIR) celltype = ID($fair);
+			if (type == AST_COVER) celltype = ID($cover);
 
 			log_assert(children.size() == 2);
 
@@ -1471,16 +1462,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				en = current_module->ReduceBool(NEW_ID, en);
 
 			IdString cellname;
-			if (str.empty()) {
-				std::stringstream sstr;
-				sstr << celltype << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
-				cellname = sstr.str();
-			} else {
+			if (str.empty())
+				cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++);
+			else
 				cellname = str;
-			}
 
 			RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
-			cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+			cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
@@ -1488,8 +1476,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 
-			cell->setPort("\\A", check);
-			cell->setPort("\\EN", en);
+			cell->setPort(ID::A, check);
+			cell->setPort(ID::EN, en);
 		}
 		break;
 
@@ -1525,9 +1513,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
 
 			RTLIL::Cell *cell = current_module->addCell(str, "");
-			cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+			cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
 			// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
-			cell->set_bool_attribute("\\module_not_derived");
+			cell->set_bool_attribute(ID::module_not_derived);
 
 			for (auto it = children.begin(); it != children.end(); it++) {
 				AstNode *child = *it;
@@ -1575,29 +1563,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
-			if (cell->type == "$specify2") {
-				int src_width = GetSize(cell->getPort("\\SRC"));
-				int dst_width = GetSize(cell->getPort("\\DST"));
-				bool full = cell->getParam("\\FULL").as_bool();
+			if (cell->type == ID($specify2)) {
+				int src_width = GetSize(cell->getPort(ID::SRC));
+				int dst_width = GetSize(cell->getPort(ID::DST));
+				bool full = cell->getParam(ID::FULL).as_bool();
 				if (!full && src_width != dst_width)
 					log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
-				cell->setParam("\\SRC_WIDTH", Const(src_width));
-				cell->setParam("\\DST_WIDTH", Const(dst_width));
+				cell->setParam(ID::SRC_WIDTH, Const(src_width));
+				cell->setParam(ID::DST_WIDTH, Const(dst_width));
 			}
-			else if (cell->type ==  "$specify3") {
-				int dat_width = GetSize(cell->getPort("\\DAT"));
-				int dst_width = GetSize(cell->getPort("\\DST"));
+			else if (cell->type ==  ID($specify3)) {
+				int dat_width = GetSize(cell->getPort(ID::DAT));
+				int dst_width = GetSize(cell->getPort(ID::DST));
 				if (dat_width != dst_width)
 					log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
-				int src_width = GetSize(cell->getPort("\\SRC"));
-				cell->setParam("\\SRC_WIDTH", Const(src_width));
-				cell->setParam("\\DST_WIDTH", Const(dst_width));
+				int src_width = GetSize(cell->getPort(ID::SRC));
+				cell->setParam(ID::SRC_WIDTH, Const(src_width));
+				cell->setParam(ID::DST_WIDTH, Const(dst_width));
 			}
-			else if (cell->type == "$specrule") {
-				int src_width = GetSize(cell->getPort("\\SRC"));
-				int dst_width = GetSize(cell->getPort("\\DST"));
-				cell->setParam("\\SRC_WIDTH", Const(src_width));
-				cell->setParam("\\DST_WIDTH", Const(dst_width));
+			else if (cell->type == ID($specrule)) {
+				int src_width = GetSize(cell->getPort(ID::SRC));
+				int dst_width = GetSize(cell->getPort(ID::DST));
+				cell->setParam(ID::SRC_WIDTH, Const(src_width));
+				cell->setParam(ID::DST_WIDTH, Const(dst_width));
 			}
 		}
 		break;
@@ -1668,19 +1656,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
 
 				Cell *cell = current_module->addCell(myid, str.substr(1));
-				cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
-				cell->parameters["\\WIDTH"] = width;
+				cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+				cell->parameters[ID::WIDTH] = width;
 
-				if (attributes.count("\\reg")) {
-					auto &attr = attributes.at("\\reg");
+				if (attributes.count(ID::reg)) {
+					auto &attr = attributes.at(ID::reg);
 					if (attr->type != AST_CONSTANT)
 						log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
-					cell->attributes["\\reg"] =  attr->asAttrConst();
+					cell->attributes[ID::reg] =  attr->asAttrConst();
 				}
 
 				Wire *wire = current_module->addWire(myid + "_wire", width);
-				wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
-				cell->setPort("\\Y", wire);
+				wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+				cell->setPort(ID::Y, wire);
 
 				is_signed = sign_hint;
 				return SigSpec(wire);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f801a17e0..45c796b07 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -172,7 +172,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		deep_recursion_warning = true;
 		while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
 
-		if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg"))
+		if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg))
 		{
 			dict<AstNode*, pool<std::string>> mem2reg_places;
 			dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags;
@@ -187,10 +187,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				bool this_nomeminit = flag_nomeminit;
 				log_assert((memflags & ~0x00ffff00) == 0);
 
-				if (mem->get_bool_attribute("\\nomem2reg"))
+				if (mem->get_bool_attribute(ID::nomem2reg))
 					continue;
 
-				if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit"))
+				if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit))
 					this_nomeminit = true;
 
 				if (memflags & AstNode::MEM2REG_FL_FORCED)
@@ -248,7 +248,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					reg->is_reg = true;
 					reg->is_signed = node->is_signed;
 					for (auto &it : node->attributes)
-						if (it.first != ID(mem2reg))
+						if (it.first != ID::mem2reg)
 							reg->attributes.emplace(it.first, it.second->clone());
 					reg->filename = node->filename;
 					reg->location = node->location;
@@ -345,9 +345,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
 					for (auto c : node->children[0]->children) {
 						if (!c->is_simple_const_expr()) {
-							if (attributes.count("\\dynports"))
-								delete attributes.at("\\dynports");
-							attributes["\\dynports"] = AstNode::mkconst_int(1, true);
+							if (attributes.count(ID::dynports))
+								delete attributes.at(ID::dynports);
+							attributes[ID::dynports] = AstNode::mkconst_int(1, true);
 						}
 					}
 				}
@@ -1219,7 +1219,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
 		wire->str = wire_id;
 		if (current_block)
-			wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+			wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 		current_ast_mod->children.push_back(wire);
 		while (wire->simplify(true, false, false, 1, -1, false, false)) { }
 
@@ -1856,7 +1856,7 @@ skip_dynamic_range_lvalue_expansion:;
 			wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
 			current_ast_mod->children.push_back(wire_tmp);
 			current_scope[wire_tmp->str] = wire_tmp;
-			wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+			wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 			while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { }
 			wire_tmp->is_logic = true;
 
@@ -2676,7 +2676,7 @@ skip_dynamic_range_lvalue_expansion:;
 					wire->is_input = false;
 					wire->is_output = false;
 					wire->is_reg = true;
-					wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+					wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 					if (child->type == AST_ENUM_ITEM)
 						wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"];
 
@@ -3364,10 +3364,10 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 	}
 
 	// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
-	if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
+	if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
 		mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
 
-	if (type == AST_MODULE && get_bool_attribute("\\mem2reg"))
+	if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
 		children_flags |= AstNode::MEM2REG_FL_ALL;
 
 	dict<AstNode*, uint32_t> *proc_flags_p = NULL;
@@ -3530,7 +3530,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		wire_addr->str = id_addr;
 		wire_addr->is_reg = true;
 		wire_addr->was_checked = true;
-		wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+		wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 		mod->children.push_back(wire_addr);
 		while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
 
@@ -3539,7 +3539,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		wire_data->is_reg = true;
 		wire_data->was_checked = true;
 		wire_data->is_signed = mem_signed;
-		wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+		wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 		mod->children.push_back(wire_data);
 		while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
 
@@ -3610,7 +3610,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			wire_addr->is_reg = true;
 			wire_addr->was_checked = true;
 			if (block)
-				wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+				wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 			mod->children.push_back(wire_addr);
 			while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
 
@@ -3620,7 +3620,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			wire_data->was_checked = true;
 			wire_data->is_signed = mem_signed;
 			if (block)
-				wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+				wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
 			mod->children.push_back(wire_data);
 			while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
 
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index cab210605..7cc157e49 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -176,7 +176,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 
 			if (!strcmp(cmd, ".blackbox"))
 			{
-				module->attributes["\\blackbox"] = RTLIL::Const(1);
+				module->attributes[ID::blackbox] = RTLIL::Const(1);
 				continue;
 			}
 
@@ -215,17 +215,17 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 					vector<Cell*> remove_cells;
 
 					for (auto cell : module->cells())
-						if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
-							module->connect(cell->getPort("\\Y"), cell->getPort("\\A"));
+						if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
+							module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
 							remove_cells.push_back(cell);
 						}
 
 					for (auto cell : remove_cells)
 						module->remove(cell);
 
-					Wire *true_wire = module->wire("$true");
-					Wire *false_wire = module->wire("$false");
-					Wire *undef_wire = module->wire("$undef");
+					Wire *true_wire = module->wire(ID($true));
+					Wire *false_wire = module->wire(ID($false));
+					Wire *undef_wire = module->wire(ID($undef));
 
 					if (true_wire != nullptr)
 						module->rename(true_wire, stringf("$true$%d", ++blif_maxnum));
@@ -337,7 +337,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				}
 
 				if (init != nullptr && (init[0] == '0' || init[0] == '1'))
-					blif_wire(q)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
+					blif_wire(q)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
 
 				if (clock == nullptr)
 					goto no_latch_clock;
@@ -356,8 +356,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 						cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
 					} else {
 						cell = module->addCell(NEW_ID, dff_name);
-						cell->setPort("\\D", blif_wire(d));
-						cell->setPort("\\Q", blif_wire(q));
+						cell->setPort(ID::D, blif_wire(d));
+						cell->setPort(ID::Q, blif_wire(q));
 					}
 				}
 
@@ -476,7 +476,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				finished_parsing_constval:
 					if (state == RTLIL::State::Sa)
 						state = RTLIL::State::S0;
-					if (output_sig.as_wire()->name == "$undef")
+					if (output_sig.as_wire()->name == ID($undef))
 						state = RTLIL::State::Sx;
 					module->connect(RTLIL::SigSig(output_sig, state));
 					goto continue_without_read;
@@ -484,23 +484,23 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 
 				if (sop_mode)
 				{
-					sopcell = module->addCell(NEW_ID, "$sop");
-					sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
-					sopcell->parameters["\\DEPTH"] = 0;
-					sopcell->parameters["\\TABLE"] = RTLIL::Const();
-					sopcell->setPort("\\A", input_sig);
-					sopcell->setPort("\\Y", output_sig);
+					sopcell = module->addCell(NEW_ID, ID($sop));
+					sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
+					sopcell->parameters[ID::DEPTH] = 0;
+					sopcell->parameters[ID::TABLE] = RTLIL::Const();
+					sopcell->setPort(ID::A, input_sig);
+					sopcell->setPort(ID::Y, output_sig);
 					sopmode = -1;
 					lastcell = sopcell;
 				}
 				else
 				{
-					RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
-					cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
-					cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
-					cell->setPort("\\A", input_sig);
-					cell->setPort("\\Y", output_sig);
-					lutptr = &cell->parameters.at("\\LUT");
+					RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
+					cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
+					cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
+					cell->setPort(ID::A, input_sig);
+					cell->setPort(ID::Y, output_sig);
+					lutptr = &cell->parameters.at(ID::LUT);
 					lut_default_state = RTLIL::State::Sx;
 					lastcell = cell;
 				}
@@ -523,32 +523,32 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 
 		if (sopcell)
 		{
-			log_assert(sopcell->parameters["\\WIDTH"].as_int() == input_len);
-			sopcell->parameters["\\DEPTH"] = sopcell->parameters["\\DEPTH"].as_int() + 1;
+			log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len);
+			sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1;
 
 			for (int i = 0; i < input_len; i++)
 				switch (input[i]) {
 					case '0':
-						sopcell->parameters["\\TABLE"].bits.push_back(State::S1);
-						sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
+						sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
+						sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
 						break;
 					case '1':
-						sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
-						sopcell->parameters["\\TABLE"].bits.push_back(State::S1);
+						sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
+						sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
 						break;
 					default:
-						sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
-						sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
+						sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
+						sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
 						break;
 				}
 
 			if (sopmode == -1) {
 				sopmode = (*output == '1');
 				if (!sopmode) {
-					SigSpec outnet = sopcell->getPort("\\Y");
+					SigSpec outnet = sopcell->getPort(ID::Y);
 					SigSpec tempnet = module->addWire(NEW_ID);
 					module->addNotGate(NEW_ID, tempnet, outnet);
-					sopcell->setPort("\\Y", tempnet);
+					sopcell->setPort(ID::Y, tempnet);
 				}
 			} else
 				log_assert(sopmode == (*output == '1'));
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 14de95e07..6f0c3fefa 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -55,37 +55,37 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 
 static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
 {
-	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
-	cell->setPort("\\A", A);
-	cell->setPort("\\Y", module->addWire(NEW_ID));
-	return cell->getPort("\\Y");
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
+	cell->setPort(ID::A, A);
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
 }
 
 static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
-	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
-	cell->setPort("\\A", A);
-	cell->setPort("\\B", B);
-	cell->setPort("\\Y", module->addWire(NEW_ID));
-	return cell->getPort("\\Y");
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_XOR_));
+	cell->setPort(ID::A, A);
+	cell->setPort(ID::B, B);
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
 }
 
 static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
-	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
-	cell->setPort("\\A", A);
-	cell->setPort("\\B", B);
-	cell->setPort("\\Y", module->addWire(NEW_ID));
-	return cell->getPort("\\Y");
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_AND_));
+	cell->setPort(ID::A, A);
+	cell->setPort(ID::B, B);
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
 }
 
 static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
-	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
-	cell->setPort("\\A", A);
-	cell->setPort("\\B", B);
-	cell->setPort("\\Y", module->addWire(NEW_ID));
-	return cell->getPort("\\Y");
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_OR_));
+	cell->setPort(ID::A, A);
+	cell->setPort(ID::B, B);
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
 }
 
 static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
@@ -241,32 +241,32 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells_) {
-			if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
-				clk_sig = it.second->getPort("\\A");
+			if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
+				clk_sig = it.second->getPort(ID::A);
 				clk_polarity = !clk_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
-				clear_sig = it.second->getPort("\\A");
+			if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
+				clear_sig = it.second->getPort(ID::A);
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
-				preset_sig = it.second->getPort("\\A");
+			if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
+				preset_sig = it.second->getPort(ID::A);
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
 			}
 		}
 	}
 
-	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
-	cell->setPort("\\A", iq_sig);
-	cell->setPort("\\Y", iqn_sig);
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
+	cell->setPort(ID::A, iq_sig);
+	cell->setPort(ID::Y, iqn_sig);
 
 	cell = module->addCell(NEW_ID, "");
-	cell->setPort("\\D", data_sig);
-	cell->setPort("\\Q", iq_sig);
-	cell->setPort("\\C", clk_sig);
+	cell->setPort(ID::D, data_sig);
+	cell->setPort(ID::Q, iq_sig);
+	cell->setPort(ID::C, clk_sig);
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 0) {
 		cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@@ -274,18 +274,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 0) {
 		cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
-		cell->setPort("\\R", clear_sig);
+		cell->setPort(ID::R, clear_sig);
 	}
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 1) {
 		cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
-		cell->setPort("\\R", preset_sig);
+		cell->setPort(ID::R, preset_sig);
 	}
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 1) {
 		cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
-		cell->setPort("\\S", preset_sig);
-		cell->setPort("\\R", clear_sig);
+		cell->setPort(ID::S, preset_sig);
+		cell->setPort(ID::R, clear_sig);
 	}
 
 	log_assert(!cell->type.empty());
@@ -324,27 +324,27 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells_) {
-			if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
-				enable_sig = it.second->getPort("\\A");
+			if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
+				enable_sig = it.second->getPort(ID::A);
 				enable_polarity = !enable_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
-				clear_sig = it.second->getPort("\\A");
+			if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
+				clear_sig = it.second->getPort(ID::A);
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
-				preset_sig = it.second->getPort("\\A");
+			if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
+				preset_sig = it.second->getPort(ID::A);
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
 			}
 		}
 	}
 
-	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
-	cell->setPort("\\A", iq_sig);
-	cell->setPort("\\Y", iqn_sig);
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
+	cell->setPort(ID::A, iq_sig);
+	cell->setPort(ID::Y, iqn_sig);
 
 	if (clear_sig.size() == 1)
 	{
@@ -353,25 +353,25 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
 
 		if (clear_polarity == true || clear_polarity != enable_polarity)
 		{
-			RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
-			inv->setPort("\\A", clear_sig);
-			inv->setPort("\\Y", module->addWire(NEW_ID));
+			RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
+			inv->setPort(ID::A, clear_sig);
+			inv->setPort(ID::Y, module->addWire(NEW_ID));
 
 			if (clear_polarity == true)
-				clear_negative = inv->getPort("\\Y");
+				clear_negative = inv->getPort(ID::Y);
 			if (clear_polarity != enable_polarity)
-				clear_enable = inv->getPort("\\Y");
+				clear_enable = inv->getPort(ID::Y);
 		}
 
-		RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
-		data_gate->setPort("\\A", data_sig);
-		data_gate->setPort("\\B", clear_negative);
-		data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+		RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
+		data_gate->setPort(ID::A, data_sig);
+		data_gate->setPort(ID::B, clear_negative);
+		data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
 
-		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
-		enable_gate->setPort("\\A", enable_sig);
-		enable_gate->setPort("\\B", clear_enable);
-		enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
+		enable_gate->setPort(ID::A, enable_sig);
+		enable_gate->setPort(ID::B, clear_enable);
+		enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
 	}
 
 	if (preset_sig.size() == 1)
@@ -381,31 +381,31 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
 
 		if (preset_polarity == false || preset_polarity != enable_polarity)
 		{
-			RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
-			inv->setPort("\\A", preset_sig);
-			inv->setPort("\\Y", module->addWire(NEW_ID));
+			RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
+			inv->setPort(ID::A, preset_sig);
+			inv->setPort(ID::Y, module->addWire(NEW_ID));
 
 			if (preset_polarity == false)
-				preset_positive = inv->getPort("\\Y");
+				preset_positive = inv->getPort(ID::Y);
 			if (preset_polarity != enable_polarity)
-				preset_enable = inv->getPort("\\Y");
+				preset_enable = inv->getPort(ID::Y);
 		}
 
-		RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
-		data_gate->setPort("\\A", data_sig);
-		data_gate->setPort("\\B", preset_positive);
-		data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+		RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
+		data_gate->setPort(ID::A, data_sig);
+		data_gate->setPort(ID::B, preset_positive);
+		data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
 
-		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
-		enable_gate->setPort("\\A", enable_sig);
-		enable_gate->setPort("\\B", preset_enable);
-		enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
+		enable_gate->setPort(ID::A, enable_sig);
+		enable_gate->setPort(ID::B, preset_enable);
+		enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
 	}
 
 	cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
-	cell->setPort("\\D", data_sig);
-	cell->setPort("\\Q", iq_sig);
-	cell->setPort("\\E", enable_sig);
+	cell->setPort(ID::D, data_sig);
+	cell->setPort(ID::Q, iq_sig);
+	cell->setPort(ID::E, enable_sig);
 
 	return true;
 }
@@ -550,13 +550,13 @@ struct LibertyFrontend : public Frontend {
 
 			if (design->has(cell_name)) {
 				Module *existing_mod = design->module(cell_name);
-				if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+				if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
 					log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
 				} else if (flag_nooverwrite) {
 					log("Ignoring re-definition of module %s.\n", log_id(cell_name));
 					continue;
 				} else {
-					log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name));
+					log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name));
 					design->remove(existing_mod);
 				}
 			}
@@ -570,7 +570,7 @@ struct LibertyFrontend : public Frontend {
 			module->name = cell_name;
 
 			if (flag_lib)
-				module->set_bool_attribute("\\blackbox");
+				module->set_bool_attribute(ID::blackbox);
 
 			for (auto &attr : attributes)
 				module->attributes[attr] = 1;
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index fb3db70d2..a23f7548e 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -216,7 +216,7 @@ struct RpcModule : RTLIL::Module {
 
 				module.second->name = mangled_name;
 				module.second->design = design;
-				module.second->attributes.erase("\\top");
+				module.second->attributes.erase(ID::top);
 				design->modules_[mangled_name] = module.second;
 				derived_design->modules_.erase(module.first);
 			}
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index ae5815f8e..519151310 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -155,7 +155,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 	Att *attr;
 
 	if (obj->Linefile())
-		attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
+		attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
 
 	// FIXME: Parse numeric attributes
 	FOREACH_ATTRIBUTE(obj, mi, attr) {
@@ -738,7 +738,7 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi
 		SigSpec dbits;
 
 		for (auto cell : candidates) {
-			SigBit bit = sigmap(cell->getPort("\\D"));
+			SigBit bit = sigmap(cell->getPort(ID::D));
 			dbits_db[bit].insert(cell);
 			dbits.append(bit);
 		}
@@ -764,7 +764,7 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi
 					if (verific_verbose)
 						log("    replacing old ff %s on bit %d.\n", log_id(old_ff), i);
 
-					SigBit old_q = old_ff->getPort("\\Q");
+					SigBit old_q = old_ff->getPort(ID::Q);
 					SigBit new_q = sig_q[i];
 
 					sigmap.add(old_q, new_q);
@@ -783,8 +783,8 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
 
 	for (auto cell : candidates)
 	{
-		SigBit clock = cell->getPort("\\CLK");
-		bool clock_pol = cell->getParam("\\CLK_POLARITY").as_bool();
+		SigBit clock = cell->getPort(ID::CLK);
+		bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
 		database[make_pair(clock, int(clock_pol))].insert(cell);
 	}
 
@@ -822,7 +822,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 	if (is_blackbox(nl)) {
 		log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
-		module->set_bool_attribute("\\blackbox");
+		module->set_bool_attribute(ID::blackbox);
 	} else {
 		log("Importing module %s.\n", RTLIL::id2cstr(module->name));
 	}
@@ -952,17 +952,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 						ascii_initdata++;
 					}
 					if (initval_valid) {
-						RTLIL::Cell *cell = module->addCell(new_verific_id(net), "$meminit");
-						cell->parameters["\\WORDS"] = 1;
+						RTLIL::Cell *cell = module->addCell(new_verific_id(net), ID($meminit));
+						cell->parameters[ID::WORDS] = 1;
 						if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound())
-							cell->setPort("\\ADDR", word_idx);
+							cell->setPort(ID::ADDR, word_idx);
 						else
-							cell->setPort("\\ADDR", memory->size - word_idx - 1);
-						cell->setPort("\\DATA", initval);
-						cell->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());
-						cell->parameters["\\ABITS"] = 32;
-						cell->parameters["\\WIDTH"] = memory->width;
-						cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
+							cell->setPort(ID::ADDR, memory->size - word_idx - 1);
+						cell->setPort(ID::DATA, initval);
+						cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
+						cell->parameters[ID::ABITS] = 32;
+						cell->parameters[ID::WIDTH] = memory->width;
+						cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
 					}
 				}
 			}
@@ -1079,7 +1079,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			}
 
 			if (initval_valid)
-				wire->attributes["\\init"] = initval;
+				wire->attributes[ID::init] = initval;
 		}
 		else
 		{
@@ -1133,8 +1133,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		SigBit bit = net_map_at(it.first);
 		log_assert(bit.wire);
 
-		if (bit.wire->attributes.count("\\init"))
-			initval = bit.wire->attributes.at("\\init");
+		if (bit.wire->attributes.count(ID::init))
+			initval = bit.wire->attributes.at(ID::init);
 
 		while (GetSize(initval) < GetSize(bit.wire))
 			initval.bits.push_back(State::Sx);
@@ -1144,7 +1144,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		if (it.second == '1')
 			initval.bits.at(bit.offset) = State::S1;
 
-		bit.wire->attributes["\\init"] = initval;
+		bit.wire->attributes[ID::init] = initval;
 	}
 
 	for (auto net : anyconst_nets)
@@ -1212,17 +1212,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 				RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
 
 				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
-						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memrd");
-				cell->parameters["\\MEMID"] = memory->name.str();
-				cell->parameters["\\CLK_ENABLE"] = false;
-				cell->parameters["\\CLK_POLARITY"] = true;
-				cell->parameters["\\TRANSPARENT"] = false;
-				cell->parameters["\\ABITS"] = GetSize(addr);
-				cell->parameters["\\WIDTH"] = GetSize(data);
-				cell->setPort("\\CLK", RTLIL::State::Sx);
-				cell->setPort("\\EN", RTLIL::State::Sx);
-				cell->setPort("\\ADDR", addr);
-				cell->setPort("\\DATA", data);
+						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
+				cell->parameters[ID::MEMID] = memory->name.str();
+				cell->parameters[ID::CLK_ENABLE] = false;
+				cell->parameters[ID::CLK_POLARITY] = true;
+				cell->parameters[ID::TRANSPARENT] = false;
+				cell->parameters[ID::ABITS] = GetSize(addr);
+				cell->parameters[ID::WIDTH] = GetSize(data);
+				cell->setPort(ID::CLK, RTLIL::State::Sx);
+				cell->setPort(ID::EN, RTLIL::State::Sx);
+				cell->setPort(ID::ADDR, addr);
+				cell->setPort(ID::DATA, data);
 			}
 			continue;
 		}
@@ -1242,21 +1242,21 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 				RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
 
 				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
-						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memwr");
-				cell->parameters["\\MEMID"] = memory->name.str();
-				cell->parameters["\\CLK_ENABLE"] = false;
-				cell->parameters["\\CLK_POLARITY"] = true;
-				cell->parameters["\\PRIORITY"] = 0;
-				cell->parameters["\\ABITS"] = GetSize(addr);
-				cell->parameters["\\WIDTH"] = GetSize(data);
-				cell->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
-				cell->setPort("\\CLK", RTLIL::State::S0);
-				cell->setPort("\\ADDR", addr);
-				cell->setPort("\\DATA", data);
+						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
+				cell->parameters[ID::MEMID] = memory->name.str();
+				cell->parameters[ID::CLK_ENABLE] = false;
+				cell->parameters[ID::CLK_POLARITY] = true;
+				cell->parameters[ID::PRIORITY] = 0;
+				cell->parameters[ID::ABITS] = GetSize(addr);
+				cell->parameters[ID::WIDTH] = GetSize(data);
+				cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
+				cell->setPort(ID::CLK, RTLIL::State::S0);
+				cell->setPort(ID::ADDR, addr);
+				cell->setPort(ID::DATA, data);
 
 				if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
-					cell->parameters["\\CLK_ENABLE"] = true;
-					cell->setPort("\\CLK", net_map_at(inst->GetClock()));
+					cell->parameters[ID::CLK_ENABLE] = true;
+					cell->setPort(ID::CLK, net_map_at(inst->GetClock()));
 				}
 			}
 			continue;
@@ -1431,7 +1431,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
 
 		if (inst->IsPrimitive() && mode_keep)
-			cell->attributes["\\keep"] = 1;
+			cell->attributes[ID::keep] = 1;
 
 		dict<IdString, vector<SigBit>> cell_port_conns;
 
@@ -1514,10 +1514,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 		for (auto wire : module->wires())
 		{
-			if (!wire->attributes.count("\\init"))
+			if (!wire->attributes.count(ID::init))
 				continue;
 
-			Const &initval = wire->attributes.at("\\init");
+			Const &initval = wire->attributes.at(ID::init);
 			for (int i = 0; i < GetSize(initval); i++)
 			{
 				if (initval[i] != State::S0 && initval[i] != State::S1)
@@ -1528,7 +1528,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			}
 
 			if (initval.is_fully_undef())
-				wire->attributes.erase("\\init");
+				wire->attributes.erase(ID::init);
 		}
 	}
 }
@@ -1652,10 +1652,10 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
 	if (GetSize(init_value) != 0) {
 		log_assert(GetSize(sig_q) == GetSize(init_value));
 		if (sig_q.is_wire()) {
-			sig_q.as_wire()->attributes["\\init"] = init_value;
+			sig_q.as_wire()->attributes[ID::init] = init_value;
 		} else {
 			Wire *w = module->addWire(NEW_ID, GetSize(sig_q));
-			w->attributes["\\init"] = init_value;
+			w->attributes[ID::init] = init_value;
 			module->connect(sig_q, w);
 			sig_q = w;
 		}
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 3f28f828d..3bffa3986 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -436,9 +436,9 @@ module_arg_opt_assignment:
 			wire->str = ast_stack.back()->children.back()->str;
 			if (ast_stack.back()->children.back()->is_input) {
 				AstNode *n = ast_stack.back()->children.back();
-				if (n->attributes.count("\\defaultvalue"))
-					delete n->attributes.at("\\defaultvalue");
-				n->attributes["\\defaultvalue"] = $2;
+				if (n->attributes.count(ID::defaultvalue))
+					delete n->attributes.at(ID::defaultvalue);
+				n->attributes[ID::defaultvalue] = $2;
 			} else
 			if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
 				ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
@@ -1511,24 +1511,24 @@ wire_name_and_opt_assign:
 		bool attr_anyseq = false;
 		bool attr_allconst = false;
 		bool attr_allseq = false;
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
-			ast_stack.back()->children.back()->attributes.erase("\\anyconst");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
+			ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
 			attr_anyconst = true;
 		}
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
-			ast_stack.back()->children.back()->attributes.erase("\\anyseq");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
+			ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
 			attr_anyseq = true;
 		}
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\allconst");
-			ast_stack.back()->children.back()->attributes.erase("\\allconst");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
+			ast_stack.back()->children.back()->attributes.erase(ID::allconst);
 			attr_allconst = true;
 		}
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\allseq");
-			ast_stack.back()->children.back()->attributes.erase("\\allseq");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
+			ast_stack.back()->children.back()->attributes.erase(ID::allseq);
 			attr_allseq = true;
 		}
 		if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
@@ -1544,7 +1544,7 @@ wire_name_and_opt_assign:
 				fcall->str = "\\$allconst";
 			if (attr_allseq)
 				fcall->str = "\\$allseq";
-			fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
+			fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
 		}
 	} |
@@ -1552,9 +1552,9 @@ wire_name_and_opt_assign:
 		AstNode *wire = new AstNode(AST_IDENTIFIER);
 		wire->str = ast_stack.back()->children.back()->str;
 		if (astbuf1->is_input) {
-			if (astbuf1->attributes.count("\\defaultvalue"))
-				delete astbuf1->attributes.at("\\defaultvalue");
-			astbuf1->attributes["\\defaultvalue"] = $3;
+			if (astbuf1->attributes.count(ID::defaultvalue))
+				delete astbuf1->attributes.at(ID::defaultvalue);
+			astbuf1->attributes[ID::defaultvalue] = $3;
 		}
 		else if (astbuf1->is_reg || astbuf1->is_logic){
 			AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
@@ -1839,7 +1839,7 @@ cell_port:
 	attr TOK_WILDCARD_CONNECT {
 		if (!sv_mode)
 			frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
-		astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
+		astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
 	};
 
 always_comb_or_latch:
@@ -1863,7 +1863,7 @@ always_stmt:
 		AstNode *node = new AstNode(AST_ALWAYS);
 		append_attr(node, $1);
 		if ($2)
-			node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false);
+			node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 	} always_cond {
@@ -1883,9 +1883,9 @@ always_stmt:
 		AstNode *node = new AstNode(AST_ALWAYS);
 		append_attr(node, $1);
 		if ($2)
-			node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false);
+			node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
 		else
-			node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false);
+			node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 		AstNode *block = new AstNode(AST_BLOCK);
@@ -2355,12 +2355,12 @@ case_type:
 
 opt_synopsys_attr:
 	opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
-		if (ast_stack.back()->attributes.count("\\full_case") == 0)
-			ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
+		if (ast_stack.back()->attributes.count(ID::full_case) == 0)
+			ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
 	} |
 	opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
-		if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
-			ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
+		if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
+			ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
 	} |
 	/* empty */;