diff options
| author | whitequark <whitequark@whitequark.org> | 2020-04-13 08:40:45 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-13 08:40:45 +0000 |
| commit | 5448f9c85d61cf1b773fc5bf041264a46d354dfa (patch) | |
| tree | c0f40207dfab55ecec8d12c2ba28182b4122e81c /frontends | |
| parent | 7f1d83c5db6201efd96a1f0d842c2ca9d671e974 (diff) | |
| parent | 8a84674a428fe2c52c711549812c9fe9ebcd8304 (diff) | |
| download | yosys-5448f9c85d61cf1b773fc5bf041264a46d354dfa.tar.gz yosys-5448f9c85d61cf1b773fc5bf041264a46d354dfa.tar.bz2 yosys-5448f9c85d61cf1b773fc5bf041264a46d354dfa.zip | |
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ilang/ilang_parser.y | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y index 91adc0cc9..0522fa72a 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/ilang/ilang_parser.y @@ -169,7 +169,7 @@ wire_stmt: current_wire->attributes = attrbuf; attrbuf.clear(); } wire_options TOK_ID EOL { - if (current_module->wires_.count($4) != 0) + if (current_module->wire($4) != nullptr) rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str()); current_module->rename(current_wire, $4); free($4); @@ -232,7 +232,7 @@ memory_options: cell_stmt: TOK_CELL TOK_ID TOK_ID EOL { - if (current_module->cells_.count($3) != 0) + if (current_module->cell($3) != nullptr) rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str()); current_cell = current_module->addCell($3, $2); current_cell->attributes = attrbuf; @@ -427,9 +427,9 @@ sigspec: delete $1; } | TOK_ID { - if (current_module->wires_.count($1) == 0) + if (current_module->wire($1) == nullptr) rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); - $$ = new RTLIL::SigSpec(current_module->wires_[$1]); + $$ = new RTLIL::SigSpec(current_module->wire($1)); free($1); } | sigspec '[' TOK_INT ']' { |