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* Merge pull request #3206 from YosysHQ/micko/quote_removeMiodrag Milanović2022-03-041-1/+4
|\ | | | | Remove quotes if any from attribute
| * Remove quotes if any from attributeMiodrag Milanovic2022-02-161-1/+4
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* | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-181-3/+31
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* verilog: support for time scale delay valuesZachary Snow2022-02-142-4/+16
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-142-6/+18
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-17/+34
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-3/+11
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* Merge pull request #3164 from zachjs/fix-ast-warnMiodrag Milanović2022-02-111-1/+1
|\ | | | | fix dumpAst() compilation warning
| * fix dumpAst() compilation warningZachary Snow2022-01-181-1/+1
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* | Add ability to override verilog mode for verific -f commandMiodrag Milanovic2022-02-091-2/+44
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* | Use bmux for NTO1MUXMiodrag Milanovic2022-02-021-16/+2
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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+127
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-2/+9
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* sv: fix size cast clipping expression widthZachary Snow2022-01-031-1/+2
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* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-2/+5
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+10
| | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
|\ | | | | Fix verific import of enum values with x and/or z
| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Update verific.ccClaire Xen2021-12-101-4/+7
| | | | | | Ad-hoc fixes/improvements
* | If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
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* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
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* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* No need to alocate more memory than usedMiodrag Milanovic2021-11-101-1/+0
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* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Add "verific -cfg" commandClaire Xenia Wolf2021-11-011-2/+75
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
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* Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-271-4/+1
| | | | This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467.
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-41/+291
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-252-24/+57
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-251-1/+4
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* Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-202-11/+45
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* Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
|\ | | | | Add support for $aldff flip-flops to verific importer
| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
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* Specify minimum bison version 3.0+Zachary Snow2021-10-012-0/+4
| | | | | | | | | Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous release). Ideally, we would require "3" rather than "3.0" to give a better error message, but bison 2.3, which still ships with macOS, does not support major-only version requirements. With this change, building with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14: require bison 3.0, but have 2.3`.
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-241-0/+1
|\ | | | | Fix "make vgtest"
| * Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
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* | sv: support wand and wor of data typesZachary Snow2021-09-211-9/+12
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-4/+10
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
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* update required verific versionMiodrag Milanovic2021-09-021-1/+1
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* sv: support declaration in generate for initializationZachary Snow2021-08-311-1/+95
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-27 22:24:40 +0000